Hi,
we are working with self-developed i.MX6 board. Now we have enabled U-Boot splash screen support. It is working well, but we have problems with LVDS interface.
If we configure LVDS we always get 56MHz LVDS clock although we configured 30MHz for LVDS clock via displays structure in the board file:
.bus = 0,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = NULL,
.enable = enable_lvds,
.mode = {
.name = "wvga-lvds",
.refresh = 57,
.xres = 800,
.yres = 480,
.pixclock = 33000,
.left_margin = 40,
.right_margin = 40,
.upper_margin = 3,
.lower_margin = 80,
.hsync_len = 10,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
Has anyone an idea what's going wrong?
Best regards,
Andreas
Hi,
Here is an example:
--- arch/arm/mach-imx/clk-imx6q.c.dist
+++ arch/arm/mach-imx/clk-imx6q.c
@@ -488,6 +488,10 @@
clk_register_clkdev(clk[IMX6QDL_CLK_GPT_3M], "gpt_3m", "imx-gpt.0");
clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
+ /* Set LDB_DI_SEL parent to be PLL5 */
+ imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+ imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
Regards