Hello everyone,
I have a problem with setting up the common clock for mac and phy of a custom i.MX6-Board:
The phy and the i.MX6 are supplied with a 50MHz clock by an external oscillator.
The connected Pin on i.MX6 is RGMII_TX_CTL.
The Interface between i.MX6 and Phy is "rmii".
Devicetree-Enty for FEC:
fec: ethernet@02188000 {
compatible = "fsl,imx6q-fec";
reg = <0x02188000 0x4000>;
interrupts-extended =
<&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "pps";
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "enet_out";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
ref-clock = <50000000>;
phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
phy-reset-duration = <2>;
fsl,magic-packet;
max-speed = <100>; /* Allow only 100MBit */
status = "okay";
};
Devicetree-Entry for IOMUX:
/* Pinmuxing for the connection to the RMII Phy */
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0f0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0f0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0f0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0f0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0f0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0f0
MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x1b0f0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0f0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0f0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0f0
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0f0 /*INTERRUPT*/
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0f0 /*RESET*/
>;
};
The Phy works fine with U-Boot, but it seems that the Linux-Kernel sets RGMII_TX_CTL as Output for the Clock.
This results in a weird "clock-collision" which makes an Ethernet Link almost impossible.
I also tried
clock-names = "ipg", "ahb", "ptp";
but with the same result.
What am I doing wrong? How can I set the RGMII_TX_CTL correctly as clock source for the i.MX6?
Solved! Go to Solution.
Well I solved the Problem:
I was not able to convince the Kernel to use the Pin as Input. So I removed the external oscillator and connected the phy directly with the clock pin of i.MX6.
Now it works very smoothly and stable.
The only thing I also had to change was the U-Boot, because the bootloader used this pin as Input and has an option for a netboot.
Now the Bootloader also uses the pin as output and can do a netboot as always.
Well I solved the Problem:
I was not able to convince the Kernel to use the Pin as Input. So I removed the external oscillator and connected the phy directly with the clock pin of i.MX6.
Now it works very smoothly and stable.
The only thing I also had to change was the U-Boot, because the bootloader used this pin as Input and has an option for a netboot.
Now the Bootloader also uses the pin as output and can do a netboot as always.
Hi Steffen
one can check in probe function of enet driver
ENET_REF_CLK, bit ENET_CLK_SEL in IOMUXC_GPR1 register.
Try with NXP Linux L4.14.98_2.0.0
linux-imx - i.MX Linux kernel
Linux L4.14.98_2.0.0 Documentation
Best regards
igor
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Hi Igor,
thanks for your answer, but I forgot to mention, that I already knew, bit 21 in IOMUXC_GPR1 is set.
My Question is more about how to write the devicetree so the kernel unsets the bit.
Or do I have to patch the Kernel?
Hi Steffen
available options through device tree are described in documentation
fsl-fec.txt\net\bindings\devicetree\Documentation - linux-imx - i.MX Linux kernel
If there are no such options one can try to patch.
Best regards
igor
That was a very nice hint!
The clocks were not correctly documented in my Kernel (4.19.56 Mainline). I changed
clock-names = "ipg", "ahb", "enet_out";
to
clock-names = "ipg", "ahb", "enet_clk_ref";
and got a clean 50MHz clock.
But now the signal seems to be too small neither for MAC or PHY. I get the error
fec 2188000.ethernet eth0: Unable to connect to phy
from Kernel.
EDIT:
IOMUXC_GPR1 0x020E0004 = 0x48601005
Bit 21 is still '1' ????