Is there any solution for SATA BIST?

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Is there any solution for SATA BIST?

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george
Senior Contributor I

Hi all,

I want to verify SATA-I/F on the i.MX6 original board.

Is it possible in i.MX6 to work the static test mode for BIST-L or BIST-TSA?

Is there any solution for it?

Best Regards,

George

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gusarambula
NXP TechSupport
NXP TechSupport

The BIST operation on the i.MX6D/Q is described on section 53.3.5.13 of the i.MX6D/Q Reference Manual (link below). The supported modes are BIST-L (Loopback) both as responder or initiator and are controlled by the register SATA_BISTCR.

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

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yaolinchang
Contributor I

Dears,

      We check kernel 3.10.17-r0 Ahci.h (Line:82~89), some sample code as below:

/* global controller registers */

  HOST_CAP = 0x00, /* host capabilities */

  HOST_CTL = 0x04, /* global host control */

  HOST_IRQ_STAT = 0x08, /* interrupt status */

  HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */

  HOST_VERSION = 0x10, /* AHCI spec. version compliancy */

  HOST_EM_LOC = 0x1c, /* Enclosure Management location */

  HOST_EM_CTL = 0x20, /* Enclosure Management Control */

  HOST_CAP2 = 0x24, /* host capabilities, extended */

We no see any destination about BIST.

Can any one give me some sample code to help to implement?

How can I enable the BIST test?

Thanks,

Best Regards,

Yao

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gusarambula
NXP TechSupport
NXP TechSupport

The BIST operation on the i.MX6D/Q is described on section 53.3.5.13 of the i.MX6D/Q Reference Manual (link below). The supported modes are BIST-L (Loopback) both as responder or initiator and are controlled by the register SATA_BISTCR.

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

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george
Senior Contributor I

Dear gusarambula,

Thanks you for your response.

Best Regards,

George

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