Interfacing SRAM with imxrt1062

[VishalAvg]

Hello everyone, I need assistance in reviewing my design. This is my first time designing with the IMXRT1062 processor.

The primary goal of my design is to interface the IMXRT1062 with external SRAM using ADMUX mode and external flash using QSPI.

I have completed the circuit design and would like to know if any changes or additions are required for the circuit to function flawlessly.

I am utilizing Latches 74HC574 to separate the address and data buses, a buffer to control read and write operations, and a decoder IC to increase chip select options for SRAM applications.

Please comments and give your valuable advice.

[VishalAvg]

Hello,

I have one more question, what is the use of configurable clock 0 and clock 1 (SEMC_CLKX0 and SEMC_CLKX1 ) ?

Is there any use of this clock signals to interface SRAM? I am using CY62126EV30LL-45ZSXI SRAM.

I attached datasheet also.

[Omar_Anguiano · Accepted solution]

These clocks are used on SYNC mode of NOR/SRAM devices. For your specific memory, there is no use of the clock signals as there is no pad for them. 

Best regards,
Omar

[VishalAvg]

Please Reply this post....

[Omar_Anguiano]

Your design looks well. It followed table 25-6 to interface the SRAM pins to RT1060. 
The capacitor on DQS pins might not be needed however this is evaluated by testing, the value is chosen by testing different capacitor values.

Best regards,
Omar

[VishalAvg]

Thank you sir for your valuable advice and suggestion.