In imx8mp processor Normal CAN is not working like sending and receiving messages are not working.

[msudagoni]

Hi All,

I am working on imxmp CAN driver with imx8mp EVK board in QNX.

observed CAN communication is not working.

Step 1: in loop back mode CAN 1 and CAN2 working in imx8mp board.

Step2: Running CAN 1 and CAN 2 with 250k baud rate.

CAN-usb FD tool from ESD connected with bitrate 250k.

dumped the Error and status register details below.

CAN MCR – 0x44a3203F here FDEN bit was not set. So CAN FD is not enabled.

CAN_CTRL – 0x6339ec04 -  the below phase seg details.

#define CAN_RJW                      0

#define CAN_PROPSEG            0x04

#define CAN_PSEG1                 0x07

#define CAN_PSEG2                 0x01

#define CAN_PREDIV_250       0x13

CAN ESR 0 0x40318 - 

bit 3 is set -  CAN flex receiving message(this i am sending from CAN tool)

bit 4-5  -  01 - error passive

bit 9 -  01- TX error warning - Tx error count is greater than or equal to 96.

bit 8 -  01 - RX error warning - Rx error count is greater than or equal to 96

Bit 18 - 01 - FlexCAN is synchronized to the CAN bus 

can you please help me here.

[Chavira]

Hi @msudagoni!

Thank you for contacting NXP Support!

Unfortunately, we don´t have experience using QNX on our boards.

QNX is not provided and supported by NXP.

You can take as a reference our Linux Driver for your driver development.

https://github.com/nxp-imx/linux-imx/tree/b586a521770e508d1d440ccb085c7696b9d6d387/drivers/net/can/f...

Sorry for the mistake!

Best Regards!

Chavira

[msudagoni]

Hi,

thanks for your reply.

is it possible to provide bit timing values and peripheral clock how much you are using in linux driver.

[Chavira]

Hi @msudagoni!

The clock assignment is declared in the device tree.

https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mp.dtsi

flexcan1: can@308c0000 {
compatible = "fsl,imx8mp-flexcan";
reg = <0x308c0000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
<&clk IMX8MP_CLK_CAN1_ROOT>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};

Best Regards!

Chavira