IS25LP032D flash settings

mrecoskie · ‎12-07-2022

Hi,

Custom RT1052 board. We are failing to commit our program over jtag. Log below.

Does someone have the flash settings for the ‘IS25LP032D’ ? I don’t see a built in driver for this.

Thanks.

Mark

Executing flash operation 'Program' (Program executable into flash evkbimxrt1050_hello_world.axf) - Wed Dec 07 16:31:40 EST 2022

Checking MCU info...

Scanning for targets...

Executing flash action...

SEGGER J-Link Commander V7.70d (Compiled Aug 30 2022 17:10:56)

DLL version V7.70d, compiled Aug 30 2022 17:10:47

J-Link Command File read successfully.

Processing script file...

J-Link>ExitOnError 1

J-Link Commander will now exit on Error

J-Link>r

J-Link connection not established yet but required for command.

Connecting to J-Link via USB...O.K.

Firmware: J-Link Pro V5 compiled Aug 30 2022 11:48:23

Hardware version: V5.00

J-Link uptime (since boot): 0d 00h 23m 23s

S/N: 175000067

License(s): RDI, FlashBP, FlashDL, JFlash, GDB

USB speed mode: High speed (480 MBit/s)

IP-Addr: DHCP (no addr. received yet)

VTref=3.335V

Target connection not established yet but required for command.

Device "MIMXRT1052XXXXA" selected.

Connecting to target via SWD

Found SW-DP with ID 0x0BD11477

DPIDR: 0x0BD11477

CoreSight SoC-400 or earlier

Scanning AP map to find all available APs

AP[1]: Stopped AP scan as end of AP map has been reached

AP[0]: AHB-AP (IDR: 0x04770041)

Iterating through AP map to find AHB-AP to use

AP[0]: Core found

AP[0]: AHB-AP ROM base: 0xE00FD000

CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)

Found Cortex-M7 r1p1, Little endian.

FPUnit: 8 code (BP) slots and 0 literal slots

CoreSight components:

ROMTbl[0] @ E00FD000

[0][0]: E00FE000 CID B105100D PID 000BB4C8 ROM Table

ROMTbl[1] @ E00FE000

[1][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table

ROMTbl[2] @ E00FF000

[2][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7

[2][1]: E0001000 CID B105E00D PID 000BB002 DWT

[2][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7

[2][3]: E0000000 CID B105E00D PID 000BB001 ITM

[1][1]: E0041000 CID B105900D PID 001BB975 ETM-M7

[1][2]: E0042000 CID B105900D PID 004BB906 CTI

[0][1]: E0040000 CID B105900D PID 000BB9A9 TPIU-M7

[0][2]: E0043000 CID B105F00D PID 001BB101 TSG

Cache: Separate I- and D-cache.

I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way

D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way

Cortex-M7 identified.

Reset delay: 0 ms

Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.

ResetTarget() start

Core did not halt on flash image verification. Assuming faulty flash settings.

Halting target manually.

ResetTarget() end

AfterResetTarget() start

AfterResetTarget() end

J-Link>h

PC = 0020C74A, CycleCnt = 00000000

R0 = 402E0000, R1 = 00000080, R2 = 00000001, R3 = 00000000

R4 = 202069E0, R5 = 00000000, R6 = 00000047, R7 = 00000010

R8 = 401F4470, R9 = 20203A00, R10= 0BD0C057, R11= 00000000

R12= 00000004

SP(R13)= 20200F78, MSP= 20200F78, PSP= 00000000, R14(LR) = 0020D137

XPSR = 61000000: APSR = nZCvq, EPSR = 01000000, IPSR = 000 (NoException)

CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00

FPS0 = 00000000, FPS1 = 00000000, FPS2 = 00000000, FPS3 = 00000000

FPS4 = 00000000, FPS5 = 00000000, FPS6 = 00000000, FPS7 = 00000000

FPS8 = 00000000, FPS9 = 00000000, FPS10= 00000000, FPS11= 00000000

FPS12= 00000000, FPS13= 00000000, FPS14= 00000000, FPS15= FFFFFFFF

FPS16= 00000000, FPS17= 00000000, FPS18= 00000000, FPS19= 00000000

FPS20= 00000000, FPS21= 00000000, FPS22= 00000000, FPS23= 00000000

FPS24= 00000000, FPS25= 00000000, FPS26= 00000000, FPS27= 00000000

FPS28= 00000000, FPS29= 00000000, FPS30= 00000000, FPS31= FFFFFFFF

FPSCR= 00000000

J-Link>loadfile "/Users/mrecoskie/Documents/MCUXpressoIDE_11.6.1_8255/workspace/evkbimxrt1050_hello_world/Debug/evkbimxrt1050_hello_world.hex"

'loadfile': Performing implicit reset & halt of MCU.

ResetTarget() start

Core did not halt on flash image verification. Assuming faulty flash settings.

Halting target manually.

ResetTarget() end

AfterResetTarget() start

AfterResetTarget() end

Downloading file [/Users/mrecoskie/Documents/MCUXpressoIDE_11.6.1_8255/workspace/evkbimxrt1050_hello_world/Debug/evkbimxrt1050_hello_world.hex]...

****** Error: Timeout while preparing target, core does not stop. (PC = 0x2000017A, XPSR = 0x41000000, SP = 0x20000B18)!

Failed to perform RAMCode-sided Prepare()

Unspecified error -1

Script processing completed.

Unable to perform operation!

Command failed with exit code 1

mrecoskie · ‎01-12-2023

This project will not run directly on our custom board. It appears to be aimed at the evaluation board.

I have successfully run a similar (if not the same project) on our evaluation board (with hardware modifications for qspi).

Some questions -

> Are any RAM setting changes (removals?) required in the project for XIP QSPI?

> What modifications are necessary to change QSPI flash sizes - for example, 32MB versus 64Mb? (our board uses the IS25LP032D versus the IS25LP064D in the samples). I also see the maximum speeds vary per chip.

Thanks.

jingpan · ‎01-15-2023

Hi @mrecoskie ,

> Are any RAM setting changes (removals?) required in the project for XIP QSPI?

No.

> What modifications are necessary to change QSPI flash sizes - for example, 32MB versus 64Mb?

They are same I think. Same QE bit, same command, same dummy byte at 100M.

If you use MCUBootUtility to download a led_blinky like application, can it work? The tool should replace FCB header with a new one.

Make the flexspi_nor_polling demo run in RAM, can it read/write IS25LP032D?

Regards,

Jing

mrecoskie · ‎01-16-2023

Thanks for the guidance. Both the flexspi_nor_polling demo and flash_component_nor demo work as expected. So it would appear the flash is working.

I’ve shifted my focus to the memory setup of the XIP application. Since we have no external RAM I've placed the stack and heap in SRAM_DTC. Yet we still seem to jump to address 0 after the SystemInit() returns. If I comment out SystemInitHook() the code executes farther until the data_load but eventually stops there. Wondering if there is some FlexRAM requirement missing?

I read a DCD initialization for SDRAM is required for for Debugging. When I trace the code I see SDRAM (0x80000000) in the memory setup before my program main. Is this expected?

Beyond that many of the variables are optimized out.

mrecoskie · ‎01-17-2023

I got this to work by moving the SDRAM and NCACHE memory definitions to the end of the list. Strangely removing these lines did not work.

Can anyone provide an explanation as to why this was the solution?

jingpan · ‎01-18-2023

Hi @mrecoskie ,

If you put SDRAM behind ITCM/DTCM, compiler will put .data/.bss segment into SDRAM. When debugging, IDE will also access SDRAM. But the SDRAM is not initialized at this time. You need a script to initialize SDRAM first.

Regards,

Jing