IRQ handler for iMX8 SCU GPIO

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IRQ handler for iMX8 SCU GPIO

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sbertrand
Contributor III

Hi,

The SCU SCFW porting kit provides different APIs.

I would like to enable interrupt on GPIO in the SCU firmware ( SCFW).

The board init of iMX8QM MEK uses FGPIO_PinInit to handle SCU GPIO.

The driver library has FGPIO_ClearPinsInterruptFlags to clean the interrupt.

How to I enable the interrupt ?

The documentation has the following example, but the function to set interrupt is not there. Which IRQ would correspond ?

```

PORT_SetPinInterruptConfig(BOARD_SW2_PORT, BOARD_SW2_FGPIO_PIN, kPORT_InterruptFallingEdge);
NVIC_EnableIRQ(BOARD_SW2_IRQ);

```

Would this functionality be handled via the SVC service of the SCFW ?

If interrupt are not available on SCU GPIO, how would I used IGPIO driver interrupt? how the IRQ is process for those GPIO ?

Regards,
Stan

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1 解決策
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sbertrand
Contributor III

The Rapid GPIO on the SCU do not support interrupt as mentioned for the M4 complex : https://community.nxp.com/thread/523693 

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sbertrand
Contributor III

The Rapid GPIO on the SCU do not support interrupt as mentioned for the M4 complex : https://community.nxp.com/thread/523693 

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jimmychan
NXP TechSupport
NXP TechSupport

Could you tell me which version of BSP are you using?

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sbertrand
Contributor III

Hi,

I am using the SCFW porting kit 1.2.9 version for scfw_export_mx8qm_b0 : imx-scfw-porting-kit-1.2.9

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jimmychan
NXP TechSupport
NXP TechSupport
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sbertrand
Contributor III

Does the 1.2.7.1 has SCU GPIO interrupt support ?

Which IRQ routine handles the GPIO interrupt ?

Is there a user function available to add custom handling for GPIO interrupt ?

Regards,
Stan

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jimmychan
NXP TechSupport
NXP TechSupport

Take arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts as a reference.

 

For the PCI node we have:

 

&pcieb{
ext_osc = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcieb>;
clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>;
disable-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>;
reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>;
epdev_on-supply = <&epdev_on>;
status = "okay";
};

 

pinctrl_pcieb defines the GPIOs used to control PCI and are defined like:

 

pinctrl_pcieb: pcieagrp{
fsl,pins = <
SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021
SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021
SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x06000021
>;
};

 

Is this the kind of example that you are looking for?

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sbertrand
Contributor III

Hi,

This is not what I am looking for. 

I am looking for SCU firmware bare metal code to support native SCU gpio block interrupt.

The device tree is not helpful with the bare metal code for the SCU firmware.

Regards,

Stan

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