IMX8ULP: Assign a peripheral from M33 to A35

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IMX8ULP: Assign a peripheral from M33 to A35

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mirkoardinghi1
Contributor IV

Hi, is possible to move a peripheral assigned to M33 core ?

For example gpio bank a/b/c are assigned to M33 core and if I want to use from A35 I need to use the fsl,imx-rpmsg-gpio driver but M33 is the controller.

Is possibile to assign these gpio directly to A35 core?

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Alejandro_Salas
NXP TechSupport
NXP TechSupport

Hello @mirkoardinghi1 

 

You can refer to IMX8ULP Reference Manual in section 2.1.3 Architecture diagram.

There you can see the Domains of cores:

Alejandro_Salas_0-1710519548488.png

As you can see, the the only peripherals accessible for cortex A are (check dts

ethernet0 = &fec;
gpio4 = &gpiod;
gpio5 = &gpioe;
gpio6 = &gpiof;
i2c4 = &lpi2c4;
i2c5 = &lpi2c5;
i2c6 = &lpi2c6;
i2c7 = &lpi2c7;
mmc0 = &usdhc0;
mmc1 = &usdhc1;
mmc2 = &usdhc2;
serial0 = &lpuart4;
serial1 = &lpuart5;
serial2 = &lpuart6;
serial3 = &lpuart7;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
isi0 = &isi_0;
csi0 = &mipi_csi0;

 

And here the accesibles for M core (Included GPIO A, B, C and I2S0):

Alejandro_Salas_1-1710519732212.png

 

As the peripherals are from different domain (Real time domain for M core and Application domain for A core) all the peripherals are not accessible for A core.

 

Best regards.

 

Salas.

 

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Alejandro_Salas
NXP TechSupport
NXP TechSupport

Hello @mirkoardinghi1 

 

I hope you are doing well.

Have you tried assigning the those GPIOs in device tree?

 

Best regards.

 

Salas.

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mirkoardinghi1
Contributor IV

Hi, yes I can assign with, for example  with bank c,

rpmsg_gpioc: gpio@2 {
compatible = "fsl,imx-rpmsg-gpio";
port_idx = <2>;
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&rpmsg_gpioc>;
status = "okay";
};

but this gpio use a special drive that demands the control to M33, I would like to use the banks a,b,c like the others

Same problem with I2S0 controlled by M33

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747 Views
Alejandro_Salas
NXP TechSupport
NXP TechSupport

Hello @mirkoardinghi1 

 

You can refer to IMX8ULP Reference Manual in section 2.1.3 Architecture diagram.

There you can see the Domains of cores:

Alejandro_Salas_0-1710519548488.png

As you can see, the the only peripherals accessible for cortex A are (check dts

ethernet0 = &fec;
gpio4 = &gpiod;
gpio5 = &gpioe;
gpio6 = &gpiof;
i2c4 = &lpi2c4;
i2c5 = &lpi2c5;
i2c6 = &lpi2c6;
i2c7 = &lpi2c7;
mmc0 = &usdhc0;
mmc1 = &usdhc1;
mmc2 = &usdhc2;
serial0 = &lpuart4;
serial1 = &lpuart5;
serial2 = &lpuart6;
serial3 = &lpuart7;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
isi0 = &isi_0;
csi0 = &mipi_csi0;

 

And here the accesibles for M core (Included GPIO A, B, C and I2S0):

Alejandro_Salas_1-1710519732212.png

 

As the peripherals are from different domain (Real time domain for M core and Application domain for A core) all the peripherals are not accessible for A core.

 

Best regards.

 

Salas.

 

726 Views
mirkoardinghi1
Contributor IV
Thanks for the clarifications