IMX8QM DDR PMU EVENTS DESCRIPTION

[mnaciri]

Hello,

We are trying to use the PMU of DDRC on the IMX8QM board.

Using the manual "i.MX 8QuadMax Applications Processor Reference Manual, Rev. 0, 9/2021", on section "10.2.3.1.3.3 Fields", we se a list of events that can be configured for each counter.

We are asking for a description of these events listed there.

For example:

....

8’h09: waq_wcount_0 == counter_1_cp[3:0]
8’h10: lpr_credit_cnt == counter_1_cp[6:0]
8’h11: hpr_credit_cnt == counter_1_cp[6:0]
8’h12: wr_credit_cnt == counter_1_cp[6:0]
8’h20: perf_hif_rd
8’h21: perf_hif_wr
8’h22: perf_hif_rmw
8’h23: perf_hif_hi_pri_rd
8’h24: perf_hpr_req_with_nocredit

...

We don't know what each of the events count, we did not found any description on the document.

Could provide more information aboute ALL the events listed on the manual, documentation or description of what count each one of them, or where we can find more information about them.

Thanks for all.

BR,

Mouad

[AldoG]

Hello,

Please see below:

WAQ_COUNT_0[3:0]: the number of used positions in the write queue FIFO
WAQ_POP_0: one write granted by port arbiter
RAQ_WCOUNT_0[3:0]: number of used positions in the read queue
RAQ_POP_0: one read granted by port arbiter
LPR_CREDIT_CNT[6:0]: number of available low priority read CAM slots free
HPR_CREDIT_CNT[6:0]: number of available high priority read CAM slots free
WR_CREDIT_CNT[6:0]: number of available write CAM slots free
stat_ddrc_reg_selfref_type[1:0] self-refresh status and type
o 00 not in self refresh
o 11 self-refresh by automatic
o 10 caused by SW/HW interface
perf_hif_rd: asserts for every read command to the DDRC
perf_hif_wr: asserts for every write command to the DDRC
perf_hif_rmw: asserts for every read modify write to the DDRC
perf_hif_hi_pri_rd: asserts for every high priority read
perf_hpr_req_with_nocredit: asserts when there is a high priority read request not served due
to no available credit
perf_hpr_xact_when_critical: asserts for every high priority read transaction that is scheduled
when the high priority queue is in critical state
perf_lpr_req_with_nocredit: asserts when there is a low priority read request not served due to
no available credit
perf_lpr_xact_when_critical: asserts for every low priority read transaction that is scheduled
when the low priority queue is in critical state
perf_wr_xact_when_critical: asserts for every write transaction that is scheduled when the write
queue is in critical state
perf_dfi_rd_data_cycles: assert for every read data cycle
perf_dfi_wr_data_cycles: assert for every write data cycle
perf_rdwr_transitions: assert for every read->write or write->read transition
perf_op_is_precharge: assert for every precharge command issued
perf_op_is_activate: assert for every active command issued
perf_op_is_load_mode: assert for every MRW or MRR command issued
perf_op_is_mwr: assert for every masked write command issued
perf_op_is_rd: assert for every read command issued
perf_op_is_rd_activate: assert for every read active issued
perf_op_is_refresh: assert for every refresh command issued
perf_op_is_wr: assert for every write command issued
perf_raw_hazard: asserts for every read-after-write collision that happens in the controller
axi_read_op: asserts for every valid axi read access
axi_write_op: asserts for every valid axi write access

Hope this helps,
Best regards/Saludos,
Aldo.

[mnaciri]

Hi Aldo,

Thanks for the answer.

We would know if there is any documentation related to this, we may need to refer/cite to it on our documentation.

Also we want to know if there are more events available, as there are missing/strided numbers on the lists.

We are intereseted on events like:

-Page hits

-Page misses

-Refresh operations

Could provided information about those.

Thanks

Mouad

[AldoG]

Hello,

There is a request to add this information to the reference manual, unfortunately we do not have a due date for this nor have more information I can share.

Thank you,
Best regards/Saludos,
Aldo.