IMX8M PLUS: GPIO Interrupt conflicts beetween M7 and A53

[aditya_yantra]

Hello,

Application: We want to use GPIOs with rising & falling edge interrupt on M7.

Problem:

It works when we halt uboot and run M7 binary. But when we boot with linux, Linux kernel panics.

So, we have disable unused and conflicting GPIOs from Device Tree. But the problem still occures. (Note: We cannot block whole "&gpio" node in device tree, as other hardware peripherals are using some gpio pins. some with interrupt and some without interrupt.)

Then we have used RDC with RDC_SEMA42 to temporary lock GPIO Port access on Linux.

Now, what happens is that, when interrupt gets from specific pins, M7 and A53 both calls IRQ. As a result, Linux kernel panics beacause we have blocked GPIO Port access from RDC. Linux Terminal Output is as follows:

[   37.410397] Internal error: synchronous external abort: 96000210 [#1] PREEMPT SMP
[   37.417885] Modules linked in: usb_f_rndis u_ether bluetooth ecdh_generic ecc rfkill crct10dif_ce snd_soc_imx_cdnhdmi snd_soc_hdmi_codec imx_sdma lm75 libcomposite configfs galcore(O)
[   37.434250] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G           O      5.4.193-5.7.2-devel+git.b60d3160fd04 #1
[   37.444159] Hardware name: Toradex Verdin iMX8M Plus WB on Verdin Development Board (DT)
[   37.452247] pstate: a0000085 (NzCv daIf -PAN -UAO)
[   37.457043] pc : mx3_gpio_irq_handler+0x3c/0xe8
[   37.461574] lr : generic_handle_irq+0x24/0x38
[   37.465926] sp : ffff800010003f60
[   37.469237] x29: ffff800010003f60 x28: ffff8000117f2080
[   37.474548] x27: 0000000000000000 x26: ffff800010004000
[   37.479858] x25: ffff800010000000 x24: 0000000000000018
[   37.485168] x23: 0000000000000001 x22: 0000000000000000
[   37.490479] x21: ffff0000f83acc58 x20: ffff0000f8dfa880
[   37.495789] x19: ffff80001181e160 x18: 0000000000000000
[   37.501099] x17: 0000000000000000 x16: 0000000000000000
[   37.506409] x15: 0000000000000000 x14: 0000000000000000
[   37.511719] x13: 0000000000000001 x12: 0000000000000002
[   37.517029] x11: 071c71c71c71c71c x10: 0000000000000040
[   37.522339] x9 : ffff8000118018e8 x8 : ffff8000118018e0
[   37.527649] x7 : ffff0000f60002c0 x6 : 0000000000000000
[   37.532959] x5 : ffff0000f6000248 x4 : 0000000000000000
[   37.538269] x3 : 0000000000000000 x2 : ffff80001195cd30
[   37.543579] x1 : 0000000000000018 x0 : ffff800012a70018
[   37.548889] Call trace:
[   37.551337]  mx3_gpio_irq_handler+0x3c/0xe8
[   37.555518]  generic_handle_irq+0x24/0x38
[   37.559528]  __handle_domain_irq+0x60/0xb8
[   37.563622]  gic_handle_irq+0x5c/0x148
[   37.567369]  el1_irq+0xb8/0x180
[   37.570510]  cpuidle_enter_state+0x84/0x360
[   37.574691]  cpuidle_enter+0x34/0x48
[   37.578265]  call_cpuidle+0x18/0x38
[   37.581751]  do_idle+0x1e4/0x288
[   37.584978]  cpu_startup_entry+0x20/0x80
[   37.588901]  rest_init+0xd4/0xe0
[   37.592128]  arch_call_rest_init+0xc/0x14
[   37.596135]  start_kernel+0x408/0x440
[   37.599799] Code: f9400a80 f9400441 b9401821 8b010000 (b9400000)
[   37.605896] ---[ end trace 6d25bb48dcb446ec ]---
[   37.610511] Kernel panic - not syncing: Fatal exception in interrupt
[   37.616863] SMP: stopping secondary CPUs
[   37.621072] Kernel Offset: disabled
[   37.624558] CPU features: 0x00002,2000200c
[   37.628651] Memory Limit: none
[   37.631706] ---[ end Kernel panic - not syncing: Fatal exception in interrupt ]---

Question:

1. Can we use GPIO pins as interrupt on M7? (It is possible, but I want to know it is advisable or not because A53 is also using IRQ and it will conflict if both will try to access IRQ Register at a same time.)
2. Do I have to make any changes to Linux Kernel Source Code to make it work?
3. Since I am using RDC as semaphone, do I have to configure Linux Source to make RDC (as semaphone) work properly on A53 ?

Thanks,

Aditya 

Attachments:

1. sourcecode.c - M7 Source Code

Usefull Details:

• Machine Details: Toradex Verdin iMX8M Plus WB 1.1A on Verdin Development Board
• Linux Kernel Details: Linux version 5.4.193-5.7.2-devel+git.b60d3160fd04 (oe-user@oe-host) (gcc version 9.5.0 (GCC)) #1 SMP PREEMPT Fri Dec 23 15:47:24 UTC 2022

[aditya_yantra · Accepted solution]

Thanks @Rita_Wang for the support.

We have to changes routing of our Custom Carrier Board and disable whole banks - &gpio3 and &gpio4 in Device Tree to make GPIO Interrupt work on Cortex-M7. There are many ways to solve this issue which can be found in following reference link.

...

Reference:

I have posted similiar thread on Toradex Community:

IMX8M PLUS: GPIO Interrupt conflicts between M7 and A53 - Technical Support - Toradex Community

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Solved: Re: imx8mm M4 vs Linux gpio interrupt flag clear - NXP Community

Solved: libgpiod with Linux gpio-imx-rpmsg.c driver - NXP Community

IMX8M Mini: Sharing GPIO block between A53 and M4 - NXP Community

[Rita_Wang]

A53 and M7 can access different IO pins in the same group without conflict because it will be handled by the bus arbitrator.

Different IO pins in the same group shall the same interrupt which can not be assigned to both A53 and M7 at the same time. When an IO group interrupt is assigned to A53, it can not be handled by M7anymore, vice versa. When an IO interrupt shall be handled in time, it can be assigned to M7 and the status of IOs assigned to A53 can be sent from M7 to A53 with RPMsg.

You can use the dts with RPMsg