IMX6ULL ESPI Slave Mode Data Missing

[j_george]

Brief of the Issue

We are testing SPI slave mode communication on iMX6ULL using the Colibri Evaluation Board. The observation is that some bytes – supposed to be sent by the slave device – are missing and not seen on the MISO line.

 Setup

1. An ESP8266 is configured as the SPI master, with a clock frequency of 125kHz. The master simply sends a set number of bytes over SPI.
2. The Colibri device contains an image that has a custom device driver which configures the SPI registers (slave mode), and just sends some bytes to the master with some data with  pre-defined values. The TX FIFO is filled with 32 words of data initially as a part of configuration..
3. The SPI bus only contains one slave. CS pin is connected to GND so that the device is always active.

Description of the Issue

The slave device receives all the bytes sent by the master. However, in the response data sent by the slave device, some words are missing and zeros are received instead of the actual data.

There are two observations associated with the issue:

1. First two words received on the bus are missing and zeros are received instead.
2. After the first two words, every next 256th word is missing and zero is received instead.

The following table shows the first observation.

Data Put into Slave (i.MXULL) TX FIFO	Data Seen on the MISO line
aa bb cc 01	00 00 00 00
aa bb cc 02	00 00 00 00
aa bb cc 03	aa bb cc 03
aa bb cc 04	aa bb cc 04

The first observation is consistent across resets, and the second one across every cycle of 256 words.

The data was analyzed from the master device, using a logic analyzer and scope.

Please note that we are not using the standard Linux driver in our case, we have a simple driver that configures the registers and fills up the TXFIFO. When there are 16 words in RXFIFO read them and fill TXFIFO with 16 words. This is the logic. 

Debugging Steps Performed

1. Changing the SPI clock frequency. No difference observed.
2. Tweaking the SPI register configuration. No difference observed.
3. Running the experiment at varied CPU loads, including 100% load. No difference observed.
4. Check the SPI FIFO configuration, interrupt handling, DMA configuration, do driver code review, test with different data patterns.  : Everything has been tried out. Could not fix the issue.
5. “SPI slave mode on i.MX6UL is affected by errata ERR009535, the burst completion by SS signal in slave mode is not functional” as per ERR009535 in the errata. Went through the errata, and confirmed that it does not apply to our issue as we are not de-asserting the SS line at any time. The slave is always kept active. Burst length is set to 32 bits, and the master transmits data continuously.
6. The TX FIFO is never empty, since it is filled initially and for every read from the RX FIFO, we are filling the TX FIFO also with data.
7. We checked if any of the flags like TXFIFO Empty, RXFIFO FULL, etc. are asserted, but none observed. 
8. The register configuration is attached. The dividers are configured properly.