IMX6UL ECSPI only sends 8 bits

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IMX6UL ECSPI only sends 8 bits

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justinwave
Contributor I

I am using a custom board modeled off the IMX6UL evk board and am using the 4.9.11 fsl release kernel. I have a device attached to ECSPI 1. The device registers and I am able to open the device from a user application. However, when I attempt to read or write to the device, I only see 8 bits are transfered, not the 32 bits that the device is expecting. So, for each read and write I perform, only the first byte of the message is actually sent. The clock and the chip select appear to be correct while the 8 bits are transferred.

Do I need to set the ECSPI1_CONREG[20:31] burst length to 32 bits in a word? And if so, do you have any references or examples on how to do this? Or any other ideas that may be causing this?

Thank you

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi justinwave

one can check patch and community activities on

spi-imx: imx6q add single burst transfer support - Patchwork 

https://community.nxp.com/thread/309866 

If you want the SS always be asserted during a transfer, you should configure the cs pin as gpio in the dts.
For example:
MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11        0x80000000

Best regards
igor
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igorpadykov
NXP TechSupport
NXP TechSupport

Hi justinwave

one can check patch and community activities on

spi-imx: imx6q add single burst transfer support - Patchwork 

https://community.nxp.com/thread/309866 

If you want the SS always be asserted during a transfer, you should configure the cs pin as gpio in the dts.
For example:
MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11        0x80000000

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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