Hello
On our custom board we use a Spansion S34MS02G1 NAND. But u-boot (fslc-2015-10) can not find it.
CPU: Freescale i.MX6SX rev1.2 at 792MHz
CPU: Industrial temperature grade (-40C to 105C) at 42C
Reset cause: POR
Board: TEM IMX6SX Modul
I2C: ready
DRAM: 256 MiB
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
NAND: 0 MiB
Our config file:
/* NAND */
#define CONFIG_CMD_NAND
#define CONFIG_NAND_MXS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* DMA stuff, needed for GPMI/MXS NAND support */
#define CONFIG_APBH_DMA
#define CONFIG_APBH_DMA_BURST
#define CONFIG_APBH_DMA_BURST8
/* MTD/UBI/UBIFS config */
#define CONFIG_LZO
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_RBTREE
On linux there is no problem:
nand: device found, Manufacturer ID: 0x01, Chip ID: 0xaa
nand: AMD/Spansion S34MS02G1
nand: 256MiB, SLC, page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
2 ofpart partitions found on MTD device gpmi-nand
Creating 2 MTD partitions on "gpmi-nand":
0x0000005a0000-0x0000069a0000 : "root"
0x0000069a0000-0x000007da0000 : "data"
Has somebody any idea?
Peter
已解决! 转到解答。
Hi
I found the problem. First the pin mux for ALE signal was wrong and I add follow patch. Now it works :smileyhappy:
Thanks for help
Index: git/arch/arm/cpu/armv7/mx6/clock.c
===================================================================
--- git.orig/arch/arm/cpu/armv7/mx6/clock.c 2015-11-24 10:06:02.814884669 +0100
+++ git/arch/arm/cpu/armv7/mx6/clock.c 2015-11-24 10:06:03.442884668 +0100
@@ -47,6 +47,17 @@
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+#ifdef CONFIG_MX6SX
+ clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+
+ clrsetbits_le32(&imx_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
+ cfg);
+
+ setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+#else
clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
clrsetbits_le32(&imx_ccm->cs2cdr,
@@ -56,6 +67,7 @@
cfg);
setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+#endif
setbits_le32(&imx_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
Hi Peter,
Care to submit this fix to u-boot@lists.denx.de ? Please generate it against master branch.
Thanks,
Fabio Estevam
This fix has been applied into u-boot-imx branch and should be part of 2016.01 version, thanks:
Hi
I found the problem. First the pin mux for ALE signal was wrong and I add follow patch. Now it works :smileyhappy:
Thanks for help
Index: git/arch/arm/cpu/armv7/mx6/clock.c
===================================================================
--- git.orig/arch/arm/cpu/armv7/mx6/clock.c 2015-11-24 10:06:02.814884669 +0100
+++ git/arch/arm/cpu/armv7/mx6/clock.c 2015-11-24 10:06:03.442884668 +0100
@@ -47,6 +47,17 @@
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+#ifdef CONFIG_MX6SX
+ clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+
+ clrsetbits_le32(&imx_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
+ cfg);
+
+ setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+#else
clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
clrsetbits_le32(&imx_ccm->cs2cdr,
@@ -56,6 +67,7 @@
cfg);
setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+#endif
setbits_le32(&imx_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
NAND size is detected via the nand_flash_detect_onfi() function in both u-boot and linux. You can add some debug statements in the function and see why the size is being reported as zero. This could be due to a Spansion/AMD weirdness or one of the necessary clocks not being enabled.