Hi,
I am working with 1 I2S microphone (SPH0645LM4H) which is connected to i.MX6UL I2s Interface. I want to record audio from this mems. My device tree set up for the same is:
sound { |
compatible = "fsl,imx-audio-sph0645", |
"fsl,imx-mic-sph0645"; |
model = "sph0645-audio"; |
cpu-dai = <&sai1>; |
gpr = <&gpr 4 0x80000 0x80000>; |
};
&sai1 { |
pinctrl-names = "default"; |
pinctrl-0 = <&pinctrl_sai1>; |
/* |
* Reference block. |
* |
* Codec dependent section. |
*/ |
assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>, |
<&clks IMX6UL_CLK_SAI1>; |
assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; |
assigned-clock-rates = <0>, <12288000>; |
fsl,sai-mclk-direction-output; |
status = "okay"; |
};
i have also attached my driver file for the same.
when i run the command to record audio:
arecord -c 1 -d 5 -f S32 -r 48000 -v /home/root/test.wav
i got below error:
Recording WAVE '/home/root/test.wav' : Signed 32 bit Little Endiafsl-sai 2028000.sai: sampling rate parms_rate output rate : 48000
n, Rate 48000 Hz, Mono
fsl-sai 2028000.sai: bclk : 3072000
fsl-sai 2028000.sai: failed to derive required Rx rate: 3072000
fsl-sai 2028000.sai: ASoC: can't set 2028000.sai hw params: -22
arecord: set_params:1403: Unable to install hw params:
ACCESS: RW_INTERLEAVED
FORMAT: S32_LE
SUBFORMAT: STD
SAMPLE_BITS: 32
FRAME_BITS: 32
CHANNELS: 1
RATE: 48000
PERIOD_TIME: (85333 85334)
PERIOD_SIZE: 4096
PERIOD_BYTES: 16384
PERIODS: 4
BUFFER_TIME: (341333 341334)
BUFFER_SIZE: 16384
BUFFER_BYTES: 65536
TICK_TIME: 0
Request you to please provide inputs, what i might need to change to make it work.
Regards,
Hitesh
This no longer compiles. sound/soc/fsl/imx-sph0645.c:43:35: error: ‘struct snd_soc_pcm_runtime’ has no member named ‘cpu_dai’
43 | struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
Hi Hitesh
>fsl-sai 2028000.sai: failed to derive required Rx rate: 3072000
>fsl-sai 2028000.sai: ASoC: can't set 2028000.sai hw params: -22
one can try to find reason for these messages debugging sai driver
fsl_sai.c\fsl\soc\sound - linux-imx - i.MX Linux kernel
and using alsa drivers description in Chapter 7 Audio attached Linux Manual.
Best regards
igor
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Hi Igor,
This is i have asked previously for dey2.4. in there i was not able to receive sai_mclk 12.288Mhz thats the reason now i want to try it on dey2.6 weather it works there or not. i was expecting reply from wigros but still didnt get the response.
i have added same driver file and config to dey2.6 and getting the error.
Request you to please look into this as a reference.
https://community.nxp.com/thread/500755
Regards,
Hitesh
Hi Hitesh
that thread was already escalated to application team.
If that did not help, suggestion to proceed with help of
NXP Professional Services | NXP
Best regards
igor
HI Igor,
Thanks for your response. i will look into that and it will be great if you can help out for dey2.6 driver implementation, if i am missing something in driver file.
It will be really helpful.
Regards,
Hitesh
Hi Igor,
i debugged into driver as you said but still i am getting master clock around 45Hz but in driver its shows 12.288Mhz.
This is the updated driver code:
static int imx_sph0645_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
u32 channels = 2; //ALWAYS 2 CHANNELS params_channels(params);
u32 ratio = 0;
u64 mclk = 12288000;
u32 rate = params_rate(params); //sampling rate
dev_err(cpu_dai->dev, "sampling rate parms_rate output rate : %d \n" , rate);
u32 bclk = rate * channels * 32; //fixed to sampling rate * 64
// ratio = mclk / bclk ;
ratio = 4;
dev_err(cpu_dai->dev, "bclk : %d \n" , bclk);
dev_err(cpu_dai->dev, "ratio : %d \n" , ratio);
int ret = 0;
/* set cpu DAI configuration */
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
if (ret) {
dev_err(cpu_dai->dev, "failed to set dai fmt\n");
return ret;
}
ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, 3, 2, 32);
if (ret) {
dev_err(cpu_dai->dev, "failed to set dai tdm slot\n");
return ret;
}
ret = snd_soc_dai_set_sysclk(cpu_dai, 1, mclk, SND_SOC_CLOCK_OUT);
if (ret)
dev_err(cpu_dai->dev, "failed to set cpu sysclk\n");
return ret;
ret = snd_soc_dai_set_bclk_ratio(cpu_dai, ratio);
if (ret)
dev_err(cpu_dai->dev, "failed to set bclk ratio\n");
return ret;
}
This is the debugging ouput:
fsl-sai 2028000.sai: Entered into fsl sai set mclk rate mclk_clk[1] = 12288000Hz:
fsl-sai 2028000.sai: Entered into fsl sai set bclk with freq: 3072000 Hz
fsl-sai 2028000.sai: Entered into fsl sai set bclk mclk_clk[0] = 0Hz:
fsl-sai 2028000.sai: Entered into fsl sai set bclk mclk_clk[1] = 12288000Hz:
fsl-sai 2028000.sai: ratio 4 for freq 3072000Hz based on clock 12288000Hz
fsl-sai 2028000.sai: Entered into fsl sai set bclk id and tx : 0, id = 1:
, savediv :4
Request you to provide your inputs regarding master clock setting.
Regards,
Hitesh