Hello community,
I checking a function around MMDC of i.MX6QP.
After initialized DRAM(MDCTL[SDE_x]=1 and DRAM_RESET goed Hi and DRAM_SDCKE start working.),
Does it have some method to DRAM_RESET go to Low level?
If MDCTL[SDE_x] = 0, DRAM_SDCKE was stopping, but DRAM_RESET keep to Hi level.
If MDMISC[RST] = 1, asserted reset to MMDC, but DRAM_RESET keep to Hi level.
Does MDCTL[SDE_x] bit only perform to DRAM_RESET from low to hi level in initialization process?
To clear MMDC configuration/status registers and DRAM_RESET pin level, it must need Hard Reset?
Best regards,
Ishii.
Solved! Go to Solution.
Hi Ishii
>Does MDCTL[SDE_x] bit only perform to DRAM_RESET from low to hi level in initialization process?
right.
>To clear MMDC configuration/status registers and DRAM_RESET pin level, it must need Hard Reset?
yes. It is necessary to follow sequence described in sect. 46.4.2 MMDC initialization
i.MX 6DualPlus/6QuadPlus Applications Processor Reference Manual
Best regards
igor
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Hi Ishii
>Does MDCTL[SDE_x] bit only perform to DRAM_RESET from low to hi level in initialization process?
right.
>To clear MMDC configuration/status registers and DRAM_RESET pin level, it must need Hard Reset?
yes. It is necessary to follow sequence described in sect. 46.4.2 MMDC initialization
i.MX 6DualPlus/6QuadPlus Applications Processor Reference Manual
Best regards
igor
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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Hello Igor,
Thank you for your quick response.
I recheck MDCTL[SDE_x] bit function based on this information.
Best regards,
Ishii.