How eFUSE's USDHC_PWR_EN works.

[simon_ko]

Device : MIMX8ML6CVNKZAB (i.MX 8MP)

eMMC : SDINBDG4-8G-XI1 

Kernel : Kernel v5.15.32

uBoot : U-Boot v2022.04 

Q1. I want the reset signal to be output from the eMMC block (usdhc3) whenever i.MX reset occurs.

For this I have enabled 0x490[7] "SD power cycle enable/eMMC reset enable". (Using uboot's fuse prog command)
But it doesn't work the way I want it to. Even if i.MX is reset, eMMC is not reset.

eMMC uses uSDHC3, and eMMC RST_n pin is connected to T28 of i.MX.

Q2. There are 4 reset_b pins of USDHC3. (AG28, B8, T28, AE6)

Which pin acts as reset_b when booting ROM Code?

I registered a case on the Support portal to get an answer to this question, but I haven't received an accurate answer for over a month.

If possible, please check case number 00496347.

[Rita_Wang]

For the emmc reset is realized in the ROM when power up. Here you do not need do special set. Your connection is OK, no problem.

Wish you have a nice day

[simon_ko]

Haven't received an answer yet.
Please answer about how USDHC_PWR_EN works.

[simon_ko]

Thank you for answer.
ROM Code resets eMMC during booting, but this is SW Reset. (Card SW Reset - CMD0)
Signal is not output to actual RST_n pin.

I want the reset signal to be output to the RST_n pin.
That's why I changed the settings of eFUSE. (0x490[7] "SD power cycle enable/eMMC reset enable")
However, the reset signal was not output, so I asked a question.

[Rita_Wang]

For the emmc reset is realized in the ROM when power up. Here you do not need do special set.

the reset signal was not output in your side is normal, as for the emmc realized the reset in the power up side, in the emmc side you can see there is pull up for the emmc RST.

[simon_ko]

Thank you for your kind support.
It seems that your understanding of my question is different.

I know that eMMC is reset during ROM boot.
(It is a S/W Reset using the CMD0 command.)

I want the actual reset signal to be output from the RST_n pin.
This is for debugging purposes.

** This is why customers want to reset eMMC every boot time. **
(When initial booting, always try to proceed with eMMC reset.
When rebooting for unknown reasons (wdt, abort, kernel crash, etc...), this is to ensure that abnormal symptoms of eMMC are excluded.)

To do this, I set the USDHC_PWR_EN bit of eFUSE.
(As I said in the previous question)

However, the actual reset signal is not output.

There is no detailed description of USDHC_PWR_EN in the Reference Manual.
It just says "SD power cycle enable/eMMC reset enable 0 - No power cycle 1 - Enabled".
I wonder if this can actually output a reset signal.

[Rita_Wang]

How is your hardware connection? In our reference design for the emmc RST, we line it out as the test point not connect to the i.MX side.

[simon_ko]

We connected i.MX's T28 to eMMC's RST_n.

The rest is the same as EVK.

[simon_ko]