I'v downloaded the ARM-EABI compiler, and I succeed in compiling the odbs package.
While, I meet a problem on the UART.
it seems not recive any input.
this is all I got.
********************************************************
Diagnostics Suite (1.0) on i.MX28 evk
Build: Jan 20 2014, 11:28:52
Freescale Semiconductor, Inc.
********************************************************
Please input char to test UART input function, 'X' exit this test
Please enter x or X to confirm
After this, nothing can be done.
The defalut uart is in BANK1 26+27, my board is BANK3 2+3, I just changed the function in /src/driver/uart/stmp_uart/stmp_uart.c
color in red is what I changed.
void init_debug_uart(struct hw_module *uart, u32 baud)
{
u32 val;
stmp_debug_uart = (volatile struct stmp_serial *)uart->base;
writel(0xa0, HW_PINCTRL_MUXSEL6_SET);
writel(0x50, HW_PINCTRL_MUXSEL6_CLR);
//writel(0xf0000, HW_PINCTRL_MUXSEL7_SET); /*BANK3_PIN25 BANK3_PIN24 to GPIO */
/* check clocks */
if ((readl(CLKCTRL_XTAL_ADDR) & 0x80000000))
writel(0x80000000, CLKCTRL_XTAL_CLR_ADDR);
......
the DBUG UART just not recive the input, what's the problem?
I found it stoped in here:
char receive_char(void)
{
// If receive fifo is empty, return false
if (stmp_debug_uart->HW_UARTDBGFR & (1 << 4))
return 0xFF;
return (u8) (stmp_debug_uart->HW_UARTDBGDR & 0xFF);
}
So I use the UART printed the stmp_debug_uart->HW_UARTDBGFR and I found the value is 111001
RI TXFE RXFF TXFF RXFE BUSY DCD DSR CTS
0 0 0 1 1 1 0 0 1
I have no idea how to solve this problem , any help wil be grateful...
已解决! 转到解答。
You need set BANK3 PIN16/PIN17 as GPIO. Because ROM set PWM0,PWM1 as DUART pins.
HW_PINCTRL_MUXSEL7_SET(0xF);
HW_PINCTRL_MUXSEL6_CLR(0xF0);
HW_PINCTRL_MUXSEL6_SET(0xA0);
Grace
clear and sharp! you are so cool!!
can you give me some advices about running the ODBS on NAND flash?
I'm using the K9F2G08U0C while I use a K9F2G08R0A's ID and passed the test.
---- Running < NAND > test
Please enter y or Y to confirm
input char is: y
Reset NAND
Read NAND ID for CE0: ID for CE0, is 0xec, 0xda, 0x10, 0x95, 0x44
Samsung K9F2G08R0A 8-bit 2K page 256MB found
NAND Erase Block 0
Nand Status 0xc0
NAND Write Page 0
Nand Status 0x10
NAND Read Page 0
data verify pass
now my Question is how to run this program on NAND ?
I'm tring to make the OBDS program runing on Nand Flash.it works well in SD card.
but when I flash it into Nand with MFGTool, there no response at all ,and the MFGTool detected a HID compliant Device, which means boot from Nand have failed.
you need put obds.bin to folder OS Firmware\files and modify ucl.xml
mfg tools download updater.sb/updater_ivt.sb to IRAM, updater.sb/updater_ivt.sb will write target image to NAND.
Grace
In my Knowledge, the elf file uses the "bootlet" to add in the PowerManage features, while in OBDS, there seems no such mechanism.
I tried to use the bootlet that generate uboot.sb ,and replace the uboot with OBDS.elf file, then it did apears some information,but still failed to boot.
PowerPrep start initialize power...
Battery Voltage = 0.83V
No battery or bad battery detected!!!.Disabling battery voltage measurements./r/nJan 22 201409:41:30
FRAC 0x92925552
memory type is DDR2
Wait for ddr ready 1power 0x00820616
Frac 0x92925552
start change cpu freq
hbus 0x00000003
cpu 0x00010001
start test memory accress
ddr2 0x40000000
finish simple test
0x8050100f
finally,I solved this problem. getting this trouble is mainly because I have no sense about the bootstream stuff.
step is:
1 gcc compile an elf file
2 use elftosb turn it to sb file
3 the SD/Nand program starts.
elftosb tool needs a .bd file
while the PMU is not work, so you should have an little program to start the PMU and DDR,defined in .bd file
then you go step 2
generate a sb file
then it works.
only need to use the mfgtool?
I'v tried it .but it has no debug infomation out .the program runs normal in SD card,
my Question is :
how this chip boot ? does it like SUMSUNG 2440?the S3C2440 copy the first 4K DATA of NAND to SRAM, then run the program in SRAM, so the 4K program should copy the left DATA in NAND to DDR, then jump to DDR.
how's i.MX28 did in the bootflow?
did the ODBS support the NAND boot directly?