Getting 27Mhz from CLKOUT1 of i.MX8

[araja]

Hi,

I am trying to get a 27Mhz clock from IMX8MP_CLK_CLKOUT1

Currently, I can generate 24 MHz.

The dts file is as below:

isp@68 {
    compatible = "onnn,ap0202";
    reg = <0x68>;
    assigned-clocks = <&clk IMX8MP_CLK_CLKOUT1_SEL>;
    assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
    assigned-clock-rates = <24000000>;
    clocks = <&clk IMX8MP_CLK_CLKOUT1>;
    clock-names = "extclk";
    #clock-cells = <0>;

   }

Is there a way to get 27 MHz in place of 24 MHz?

Please advise.

Regards,

Arief

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

Could you try to change the clock parent as this post suggests?

PLL3 can be mapped as ref manual indicates.

Regards