GPIO wait states

[andresgonzalez]

Hi.

In the i.MX6 Solo reference manual it is mentioned the following for the GPIO pad status register.

Two wait states are required any time this register is accessed for synchronization.

However we don't understand what that exactly means and also if this require any special action from the software when reading the register.

If somebody can help us answering the following questions we would be very grateful.

• Does this mean that the hardware takes two wait states to synchronize  the register once the GPIO pin changed?.
• What considerations should the software take to account for these wait states?.
• How long a wait state is?.

Thanks.

[gusarambula · Accepted solution]

The legends “Two wait states are required in read access for synchronization” in regards of the GPIO Interrupt status register refers to the internal port implementation and it’s not user configurable. It refers more to the latency when it comes to interruption and required no additional actions by the software.

You may find the timing characteristics of the GPIO pins on the i.MX6S Datasheet (link below) on Figure 6 and table 28. I would take these transitions as a “wait state” sort of speak, but If I find a more well rounded definition I’ll let you know.

http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SDLCEC.pdf

[andresgonzalez]

Thanks for your help gusarambula.

In the case of the GPIO data register and GPIO pad status register, these wait times would be the time for the pin to reflect the output and for the register to reflect the input respectively. Am I right?.

Thanks for your help.