Hello,
I tried to build loopback system with i.MX6 as RC and Altera FPGA as EP.
I write data from software on Linux, then FPGA will back same data to software .
I made test program using user space I/O before making kernel driver at first.
This program was able to write data to FPGA. But I got following error at read data from FPGA.
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Unhandled fault: external abort on non-linefetch (0x1018) at
Bus error
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I am using yocto its kernel version 3.14.52-1.1.1_ga+gdb1bcba.
I set 0x01100000-0x011FFFFFF as BAR0 at FPGA.
result of lspci
01:00.0 Multimedia video controller: Altera Corporation Device 1001 (rev 01)
Subsystem: Altera Corporation Device 1001
Flags: bus master, fast devsel, latency 0, IRQ 400
Memory at 01100000 (32-bit, non-prefetchable) [size=1M]
Capabilities: [50] MSI: Enable+ Count=16/16 Maskable- 64bit+
Capabilities: [78] Power Management version 3
Capabilities: [80] Express Endpoint, MSI 00
Capabilities: [100] Virtual Channel
Capabilities: [200] Vendor Specific Information: ID=1172 Rev=0 Len=044 <?>
result of cat resource
~# cat /sys/bus/pci/devices/0000\:01\:00.0/resource
0x0000000001100000 0x00000000011fffff 0x0000000000040200
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x0000000000000000 0x0000000000000000 0x0000000000000000
A part of my source codes are following,
/*######
int barfd;
void *addrbar0;
barfd = open("/sys/class/uio/uio0/device/resource0", O_RDWR);
addrbar0 = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_SHARED, barfd, 0);
close(barfd);
/* Write to FPGA */
*(unsigned int*)(addrbar0 + cnt) = src_data[cnt];
/* Read from FPGA */
dst_data[cnt] = *(unsigned int*)(addrbar0 + cnt);
######*/
open function and mmap function was no error occurred.
When I perform writing to FPGA, then it succeeded. But when I perform reading from FPGA, then I got “Bus Error“.
What should I do?
Best Regards,
Hello,
Is it possible to check if data, written to the FPGA, really were accepted?
Have a great day,
Yuri
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Hello,
Thank you for your reply.
I checked FPGA about write back. I found that FPGA write back address was invalid.
And when I read PCI BAR0 address, then CPU make unnecessary read command to PCIe. Error might be occurred because FPGA was not acceptable.
Best Regards,