We had a working project in qbase2 karo board that used the SoM QS8M-MQ00 (i.MX8MM) & KSZ9131RNX RGMII and it has been working without a problem. We're working with yocto linux.
When trying to adapt the yocto project to our custom board we're having problems with the use of DP83867IR/CR (eth0), we've managed to ping to the network with another chip on the board an USB-Eth one using eth1.
In order to configure for use we've added the following configurations to the kernel.
CONFIG_MII=y
CONFIG_DP83867_PHY=y
We've also modified the device tree files for both the u-boot and linux. This is our .dts for the kernel, we have the same in u-boot.
#include "imx8mm-qs8m-mq00.dts"
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "TEST";
};
&fec1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec1_b &pinctrl_etnphy_rst_b>;
pinctrl-1 = <&pinctrl_fec1_b_sleep>;
phy-mode = "rgmii";
phy-handle = <ðphy1>;
phy-supply = <®_vdd_3v3>;
// phy-reset-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
// phy-reset-duration-us = <25000>;
// phy-reset-post-delay-us = <250000>;
status = "okay";
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
//rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
};
};
};
&iomuxc {
// pinctrl_etnphy_int_b: etnphy-int-bgrp {
// fsl,pins = <
// MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x90
// >;
// };
pinctrl_etnphy_rst_b: etnphy-rst-bgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x140
>;
};
pinctrl_fec1_b: fec1-bgrp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x142
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x142
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x010
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x016
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x016
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x150 /* MODE0 */
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x150 /* MODE1 */
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x150 /* MODE2 */
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x150 /* MODE3 */
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x116 /*qbase 4 0x156 */
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x116 /*qbase 4 0x156 */
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016
>;
};
pinctrl_fec1_b_sleep: fec1-b-sleep-grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
>;
};
};
We know that the RGMII chip is working because from u-boot we can actually access the mdio and read all the registers. But linux doesn't seem to be able to find the PHY. I've tried to add a static IP to u-boot and ping from there, but that's also not working. Also, when adding the rest into the .dts u-boot stops detecting the PHY, but the reset pin seems to be ok. Any ideas?
0 - Generic PHY <--> ethernet@30be0000
QS8M U-Boot > mdio list
FEC0:
0 - Generic PHY <--> ethernet@30be0000
QS8M U-Boot > mii device
MII devices: 'FEC0'
Current device: 'FEC0'
Hi @tofu,