EMMC drive not reliable

[davidzhou]

Hi,

I have imx6ul dev board and Linux 4.15 yocto

Originally, we have 4G EMMC chip on dev board, occasionally it shows errors during initialization stage:

Now we have  8G EMMC (micro Electronics) ship on production boards. The EMMC drive is not reliable at all.

it sends out many errors:

blk_update_request: I/O error, dev mmcblk1, sector 2048

mmcblk1: error -84 transferring data, sector 14941960, nr 120, cmd response 0x900, card status 0xb00

Here is the setup to the chip:

clock:          50000000 Hz                                                     
actual clock:   49500000 Hz                                                     
vdd:            21 (3.3 ~ 3.4 V)                                                
bus mode:       2 (push-pull)                                                   
chip select:    0 (don't care)                                                  
power mode:     2 (on)                                                          
bus width:      3 (8 bits)                                                      
timing spec:    8 (mmc DDR52)                                                   
signal voltage: 0 (3.30 V)

Here is the device tree configuration:

pinctrl-assert-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pinctrl_usdhc2_8databits>;
non-removable;
broken-cd;
pinctrl-names = "default";
fsl,delay-line = <0>;
no-1-8-v;
max-frequency = <50000000>;
keep-power-in-suspend;
bus-width = <8>;

What else is missing?

Any suggestions?

Thank you,

David Zhou

[robertchapin]

Hi Igor,

I am also having a similiar issue with 5.1 . It works sometimes and it  appears to work better after warming up. I have intermittent core dumps.  I am using linux-fslc-imx 4.1.4 kernel with yocto and rocko branch.

Here is the emmc part from kernel boot print out.

mmc1: new DDR MMC card at address 0001

mmcblk1: mmc1:0001 Q2J54A 3.59 GiB

mmcblk1boot0: mmc1:0001 Q2J54A partition 1 16.0 MiB

I tried changing 0x17059 to 0x17058 on all 8 pins(slew rate). Below. This DID NOT  help. Could  you pleas suggest another value to change 0x17059 to.   Not sure if you are recommending to change output drive or input  characteristics for data return? 

Here is my last device tree settings:

&usdhc4 {

      pinctrl-names = "default";

     pinctrl-0 = <&pinctrl_usdhc4_1>;

      vmmc-supply = <&reg_3p3v>;

      bus-width = <8>;

       non-removable;

       no-1-8-v;

       keep-power-in-suspend;

       status = "okay";

};

pinctrl_usdhc4_1: usdhc4grp-1 {

fsl,pins = <

MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17058

MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10058

MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17058

MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17058

MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17058

MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17058

MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17058

MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17058

MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17058

MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17058

>

Note: I also made this change even though it does not appear that this function even gets called. I put a printk in the beginning of this function and it does not print out.

/drivers/mmc/core/mmc.c :

if (card->ext_csd.rev > 6) {              // The '6' has to be replaced with '7' For EMMC5.0

                                                       //  The '6' has to be replaced with '8'  For EMMC5.1

Suggestions...please?

Rob

[igorpadykov · Accepted solution]

Hi David

one can try to tweak signal drive strength, both i.MX6 side

(using registers IOMUXC_SW_PAD_CTL_PAD_x_y described in IOMUX Chapter

of Reference Manual) and eMMC (it has special registers). Example in dts file :

linux/arch/arm/boot/dts/imx6ul-14x14-evk.dts

        pinctrl_usdhc1: usdhc1grp {
            fsl,pins = <
                MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059

linux-imx.git - i.MX Linux Kernel 

For boot one can use

"SD/MMC Pad Settings Override Selection"described in Table 8-15. USDHC Boot eFUSE Descriptions

http://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf 

Best regards
igor
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[davidzhou]

Hi Igor,

Thank you for your input.

David