During LPDDR3 enter self refresh mode, i.MX7 can be asserted reset?

[toshiharu_shimi]

I would like to hard-reset the i.MX7 processor with keeping on LPDDR3 data by self-refresh mode.
Is that possible?

I am concerned that the i.MX7 pins connected to LPDDR3, especially the "CKE" pin, may cause LPDDR3 to exit self-refresh mode.

For exsample, If the "CKE" pin outputs Hi during a hard reset or initialization, LPDDR3 exits from self-refresh mode.
During a hard reset or initialization, Does CKE pin keep Low?
And Does other pins related LPDDR3 keep the same level before reset?

[Sanket_Parekh]

Hi @toshiharu_shimi 

Hope you are doing well.

Auto-refresh logic must be enabled, or refresh should be issued using direct software requests of the refresh command via DBGCMD.rank*_refresh. This step occurs only if the DFI low power interface for self-refresh is enabled (DFILPCFG0.dfi_lp_en_sr). Attempts an entry to low power mode via DFI low power interface with dfi_lp_wakeup set by DFILPCFG0.dfi_lp_wakeup_sr.

Automatic self-refresh has lowest priority and is superseded by both software and hardware low power self-refresh. A software self-refresh entry means that a self-refresh exit occurs only if a software self-refresh exit occurs. Similarly, a hardware low power self-refresh entry means a self-refresh exit occurs only if a hardware low power self-refresh exit occurs. You can find the reference from 9.2.4.9.1.2 Self-refresh: in https://www.nxp.com/webapp/Download?colCode=IMX7DRM&_gl=1*2wrqd5*_ga*MTcyMDc0MTE4Mi4xNjk2MjI0MjUw*_g..... 

Thanks and Regards,

Sanket Parekh

[toshiharu_shimi]

Hi @Sanket_Parekh
Thank you for your reply.
After Putting the LPDDR3 device into self-refresh mode, I would like hard-reset i.MX7 by asserting _POR pin to Low.

Durring i.MX7 in hard-reset, Can LPDDR3 keep the self-refresh mode?

After i.MX7 hard-reset is released, i.MX7 send exitting self-refresh command to LPDDR3, Can i.MX7 resume running program?

[Sanket_Parekh]

Hi @toshiharu_shimi,

I hope you are doing well.

According to the DDR3 JEDEC standard, the issue of the SRX command consists of transitioning the CKE signal from Low to High with the CS# signal staying High. So, the moment of the CKE signal assertion is the moment of issuing the SRX command.

The DDRMC takes the DDR SDRAM out of self-refresh mode under the following conditions:
• Whenever the PWRCTL.selfref_en input is de-asserted, or new commands are received by the DDRMC, as long as automatic self-refresh is the only cause for self-refresh entry(STAT.selfref_auto_flag = 1).
• Whenever the PWRCTL.selfref_sw bit is de-asserted. This is referred to as software self-refresh exit.
• When a hardware low power exit request occurs (on csysreq_ddrc / csysack_ddrc).
This is referred to as hardware low power self-refresh exit.
Exiting self-refresh mode involves the following steps:
1. Inserting any NOP / deselect commands required to satisfy the tCKE / tCKERSR requirements after entering self-refresh.

2. This step occurs only if DFI low power mode entry during self-refresh entry is successful. Performs an exit from DFI low power mode.
3. Issuing the self-refresh exit command (refresh with CKE = 1).
4. Issuing NOP / deselect for the period defined by tXSDLL / tXSNR / tXSRD.

Hence, After you refer to the imx reference manual, you will conclude that it Enters Self-Refresh (CKE = 0) & Exits Self-Refresh (CKE = 1). And in addition to initializing the SDRAM after a hard reset, the initialization sequence can also be used to bring the SDRAM out of self-refresh mode.

Thanks & Regards,
Sanket Parekh