MX8MP list of peripherals available from Cortex M7

[massimo-cristofolini]

I can't find a list of pins/peripherals that can be accessed from M7 processor.

I'm using a Variscite board with MX8MP processor (VAR-SOM-MX8M-PLUS), with a Debian image provided by Variscite. I starting to play with the Cortex M7 processor (UART, GPIO (LED) and RPMsg). I'm able to blink a LED defined on the example software (GPIO3_IO14). But which other GPIO are available from M7 processor?

I loaded a DTB that "disables any peripherals that will be allocated to the Cortex M7". But which are those peripherals? Do I need to check the DTB source? Is there a list of shared peripherals that I can refer to, so I can further edit the devicetree to disable more peripherals on Linux side, so they will be available for Coretx M7?

Thanks

[massimo-cristofolini]

Thanks for the info. I'll read the docs you linked.

I'm aware that I need to setup the peripherals on M7 side. But I first need to know which one I can actually setup.

It also came to my mind that I can get back to the DTS file from the binary DTB using Linux's DTC utility. I de-compiled the DTB file and now I see which devices are in "disable" state, so which pins I can safely use on M7. I'll do further testing and report back.

[JosephAtNXP]

Hi,

Seems like a good idea, I'll look forward to your update.

Regards,

Joseph

[massimo-cristofolini]

The trick worked.

I decompiled the DTB file with this command from Linux host

$ dtc -I dtb -O dts -o imx8mp-var-som-symphony-m7.dts imx8mp-var-som-symphony-m7.dtb

imx8mp-var-som-symphony-m7.dtb is the DTB file, shipped with Variscite OS, that disables several peripherals on Debian side so the user can use them on M7.
I've also decompiled the default DTB (imx8mp-var-som-symphony.dtb) and diff-ed the two, to better understand which peripherals were disabled.

I then generated my DTS, disabling some more peripherals I didn't need to free up pins for M7. Used said pins on M7 with success. Will generate a patch when moving to Yocto, but for the moment this was a good enough solution.

Regarding my other question "Is there a list of shared peripherals that I can refer to, so I can further edit the Devicetree to disable more peripherals on Linux side, so they will be available for Cortex M7?", it looks like all the pins defined for the processor are available, as long as the OS on A53 is not using (=> disabled in Devicetree). Can you confirm me that?

[JosephAtNXP]

Hi,

You could approach that list technically in chapter 3.2 of i.MX 8M Plus Reference Manual, RDC is the module responsible for peripheral assignment.

Thank you!

[massimo-cristofolini]

Thanks for the hint!

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

You should refer to the device tree to see what are the possible modules prevention, e.g. this stationary exclusion from cortex-A. And this doesn't mean that cortex-M automatically has to use it, it should be invoked in board.h, e.g. polling_b2b_transfer master.

/*! @brief The board name */

#define BOARD_NAME        "MIMX8MP-EVK"

#define MANUFACTURER_NAME "NXP"

#define BOARD_DOMAIN_ID   (1U)

/* The UART to use for debug messages. */

#define BOARD_DEBUG_UART_TYPE     kSerialPort_Uart

#define BOARD_DEBUG_UART_BAUDRATE (115200U)

#define BOARD_DEBUG_UART_BASEADDR UART4_BASE

#define BOARD_DEBUG_UART_INSTANCE (4U)

#define BOARD_DEBUG_UART_CLK_FREQ

This is a good reference for cortex-M getting started.

Regards