Does the SRS (Software Reset Signal) Bit of the WDOG Register reset the system?

[simon_ko]

I'm reviewing WDOG on the i.MX 8M Plus.

Page 973 of IMX8MPRM Rev.1 says that WDOG generates reset signal by SRS.

However, the SRS bit description of WCR Register says that Software Reset is not generate in Block.

I don't understand this part.
Please explain.

Thanks.

[Sanket_Parekh · Accepted solution]

Hi @simon_ko ,

I hope you are doing well.

It suggests that the SRS bit doesn't not necessarily resets the system as WDOG_RESET_B_DEB doesn't generate software reset directly. unlike wdog_b which can be used to reset PMIC.

WDOG_RESET_B_DEB is given as input to SRC(refer to Figure 6-31. SRC inputs and outputs in RM)  and the Reset functionality of cores can be configured using the SRC register.

One can refer to MASK_WDOG1_RST in 6.5.5.2 A53 Reset Control Register and  6.5.5.4 M7 Reset Control Register in RM for more information,

Thanks & Regards,

Sanket Parekh