Hi,
We design a custom i.MX6ULL board that connect to a DDR3 DRAM (x16) using data pin swapping.
Host D0 <--> DRAM DQU0
Host D8 <--> DRAM DQL0
The rest of pins are swapped within the byte lane.
1) How to configure the DDR controller so that it will read/write the data content correctly?
Regards,
Bernhard.
You don't need to do anything in software, just follow the rules ...
... and the DDR controller adapts to your actual implementation.
The Note about the "DDR IC" register is not relevant here.
Regards,
Bernhard.
Hi Bernhard,
Thanks for your speedy response!
1) We are using SK Hynix DDR3L 4Gb SDRAM. The Linux BSP is from Murata Yocto project for i.MX6ULL-EVK. Need your advice if we need to modify any source code from the kernel-source?
2) Is that any configuration available for us to fine-tune the DDR speed?
Regards