DDR Test & calibration : please check my test result and is this OK? or not

[albatros74]

this is my customized I.MX6Q board. this has a problem of bring up.

so, I want to check DDR calibration and stress test.

this is full log of calibartion and stress test. but I have some question of result.

I will ask it inline. please help me.

Thank you in advance.

basic information : I.MX6Q, 1.2GH, 2GB DDR 

======================================

reading ddr-test-uboot-jtag-mx6dq.bin
121880 bytes read in 29 ms (4 MiB/s)
## Starting application at 0x00907000 ...

============================================
DDR Stress Test (3.0.0)
Build: Dec 14 2018, 14:20:05
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.5
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00003040
SRC_SBMR2(0x020d801c) = 0x22000001
============================================

What ARM core speed would you like to run?
Type 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz
ARM Clock set to 800MHz

============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 2048MB
============================================

Current Temperature: 26
============================================

Please select the DDR density per chip select (in bytes) on the board
Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for 32MB
For maximum supported density (4GB), we can only access up to 3.75GB. Type 7 to select this
DDR density selected (MB): 2048

Would do you want to change VDD_SOC_CAP/VDD_ARM_CAP voltage? Type 'y' to run and 'n' to skip

Would do you want run DDR Calibration? Type 'y' to run and 'n' to skip

Calibration will run at DDR frequency 528MHz. Type 'y' to continue.
If you want to run at other DDR frequency. Type 'n'
Please enter the MR1 value on the initilization script
This will be re-programmed into MR1 after write leveling calibration
Enter as a 4-digit HEX value, example 0004, then hit enter
0004DDR Freq: 528 MHz

///// Question 1 ////

What is the right 4 HEX value. I don't know this meaning, MR1 value is not 4 digit...
please let me know what is this valule?

I used. example value for test.

///// Question 1 ////

ddr_mr1=0x00000004
Start write leveling calibration...
running Write level HW calibration
MPWLHWERR register read out for factory diagnostics:
MPWLHWERR PHY0 = 0x3c3e3c3e
MPWLHWERR PHY1 = 0x1e3e3e3c

Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x0021001C
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x002B001E
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x00190023
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x000A001C
Write DQS delay result:
Write DQS0 delay: 28/256 CK
Write DQS1 delay: 33/256 CK
Write DQS2 delay: 30/256 CK
Write DQS3 delay: 43/256 CK
Write DQS4 delay: 35/256 CK
Write DQS5 delay: 25/256 CK
Write DQS6 delay: 28/256 CK
Write DQS7 delay: 10/256 CK

WARNING: write-leveling calibration value is greater than 1/8 CK.
Per the reference manual, WALAT must be set to 1 in the register MDMISC(0x021B0018).
This has been performed automatically.
However, in addition to updating the calibration values in your DDR initialization,
it is also REQUIRED change the value of MDMISC in their DDR initialization as follows:

MMDC_MDMISC (0x021b0018) = 0x00091740

Starting DQS gating calibration
. HC_DEL=0x00000000 result[00]=0x11111111
. HC_DEL=0x00000001 result[01]=0x11110111
. HC_DEL=0x00000002 result[02]=0x00110011
. HC_DEL=0x00000003 result[03]=0x00000000
. HC_DEL=0x00000004 result[04]=0x01000000
. HC_DEL=0x00000005 result[05]=0x11111111
. HC_DEL=0x00000006 result[06]=0x11111111
. HC_DEL=0x00000007 result[07]=0x11111111
. HC_DEL=0x00000008 result[08]=0x11111111
. HC_DEL=0x00000009 result[09]=0x11111111
. HC_DEL=0x0000000A result[0A]=0x11111111
. HC_DEL=0x0000000B result[0B]=0x11111111
. HC_DEL=0x0000000C result[0C]=0x11111111
. HC_DEL=0x0000000D result[0D]=0x11111111
DQS HC delay value low1 = 0x01020303, high1=0x04040404
DQS HC delay value low2 = 0x02020303, high2=0x04030404

loop ABS offset to get HW_DG_LOW
. ABS_OFFSET=0x00000000 result[00]=0x11111111
. ABS_OFFSET=0x00000004 result[01]=0x11111111
. ABS_OFFSET=0x00000008 result[02]=0x11011111
. ABS_OFFSET=0x0000000C result[03]=0x11001101
. ABS_OFFSET=0x00000010 result[04]=0x11001101
. ABS_OFFSET=0x00000014 result[05]=0x11001101
. ABS_OFFSET=0x00000018 result[06]=0x11001101
. ABS_OFFSET=0x0000001C result[07]=0x11001100
. ABS_OFFSET=0x00000020 result[08]=0x11001100
. ABS_OFFSET=0x00000024 result[09]=0x11111111
. ABS_OFFSET=0x00000028 result[0A]=0x11001100
. ABS_OFFSET=0x0000002C result[0B]=0x11001100
. ABS_OFFSET=0x00000030 result[0C]=0x11001100
. ABS_OFFSET=0x00000034 result[0D]=0x11001100
. ABS_OFFSET=0x00000038 result[0E]=0x11111111
. ABS_OFFSET=0x0000003C result[0F]=0x11001100
. ABS_OFFSET=0x00000040 result[10]=0x11001100
. ABS_OFFSET=0x00000044 result[11]=0x11001100
. ABS_OFFSET=0x00000048 result[12]=0x10001100
. ABS_OFFSET=0x0000004C result[13]=0x10001100
. ABS_OFFSET=0x00000050 result[14]=0x10001100
. ABS_OFFSET=0x00000054 result[15]=0x00001100
. ABS_OFFSET=0x00000058 result[16]=0x00001100
. ABS_OFFSET=0x0000005C result[17]=0x00001100
. ABS_OFFSET=0x00000060 result[18]=0x00000100
. ABS_OFFSET=0x00000064 result[19]=0x00000100
. ABS_OFFSET=0x00000068 result[1A]=0x00000100
. ABS_OFFSET=0x0000006C result[1B]=0x00000000
. ABS_OFFSET=0x00000070 result[1C]=0x00000000
. ABS_OFFSET=0x00000074 result[1D]=0x00000000
. ABS_OFFSET=0x00000078 result[1E]=0x00000000
. ABS_OFFSET=0x0000007C result[1F]=0x00000000

loop ABS offset to get HW_DG_HIGH
. ABS_OFFSET=0x00000000 result[00]=0x00000000
. ABS_OFFSET=0x00000004 result[01]=0x00000000
. ABS_OFFSET=0x00000008 result[02]=0x00000000
. ABS_OFFSET=0x0000000C result[03]=0x11111111
. ABS_OFFSET=0x00000010 result[04]=0x00000000
. ABS_OFFSET=0x00000014 result[05]=0x00000000
. ABS_OFFSET=0x00000018 result[06]=0x00000000
. ABS_OFFSET=0x0000001C result[07]=0x00000000
. ABS_OFFSET=0x00000020 result[08]=0x00000000
. ABS_OFFSET=0x00000024 result[09]=0x00000000
. ABS_OFFSET=0x00000028 result[0A]=0x00000000
. ABS_OFFSET=0x0000002C result[0B]=0x00000100
. ABS_OFFSET=0x00000030 result[0C]=0x00000100
. ABS_OFFSET=0x00000034 result[0D]=0x00001100
. ABS_OFFSET=0x00000038 result[0E]=0x10001110
. ABS_OFFSET=0x0000003C result[0F]=0x10101110
. ABS_OFFSET=0x00000040 result[10]=0x10101110
. ABS_OFFSET=0x00000044 result[11]=0x10101110
. ABS_OFFSET=0x00000048 result[12]=0x10101110
. ABS_OFFSET=0x0000004C result[13]=0x10111110
. ABS_OFFSET=0x00000050 result[14]=0x10111111
. ABS_OFFSET=0x00000054 result[15]=0x10111111
. ABS_OFFSET=0x00000058 result[16]=0x10111111
. ABS_OFFSET=0x0000005C result[17]=0x11111111
. ABS_OFFSET=0x00000060 result[18]=0x10111111
. ABS_OFFSET=0x00000064 result[19]=0x10111111
. ABS_OFFSET=0x00000068 result[1A]=0x10111111
. ABS_OFFSET=0x0000006C result[1B]=0x11111111
. ABS_OFFSET=0x00000070 result[1C]=0x10111111
. ABS_OFFSET=0x00000074 result[1D]=0x11111111
. ABS_OFFSET=0x00000078 result[1E]=0x11111111
. ABS_OFFSET=0x0000007C result[1F]=0x11111111

BYTE 0:
Start: HC=0x02 ABS=0x3C
End: HC=0x04 ABS=0x4C
Mean: HC=0x03 ABS=0x44
End-0.5*tCK: HC=0x03 ABS=0x4C
Final: HC=0x03 ABS=0x4C
BYTE 1:
Start: HC=0x02 ABS=0x3C
End: HC=0x04 ABS=0x34
Mean: HC=0x03 ABS=0x38
End-0.5*tCK: HC=0x03 ABS=0x34
Final: HC=0x03 ABS=0x38
BYTE 2:
Start: HC=0x01 ABS=0x6C
End: HC=0x04 ABS=0x28
Mean: HC=0x03 ABS=0x0A
End-0.5*tCK: HC=0x03 ABS=0x28
Final: HC=0x03 ABS=0x28
BYTE 3:
Start: HC=0x00 ABS=0x60
End: HC=0x04 ABS=0x30
Mean: HC=0x02 ABS=0x48
End-0.5*tCK: HC=0x03 ABS=0x30
Final: HC=0x03 ABS=0x30
BYTE 4:
Start: HC=0x02 ABS=0x3C
End: HC=0x04 ABS=0x48
Mean: HC=0x03 ABS=0x42
End-0.5*tCK: HC=0x03 ABS=0x48
Final: HC=0x03 ABS=0x48
BYTE 5:
Start: HC=0x02 ABS=0x3C
End: HC=0x04 ABS=0x38
Mean: HC=0x03 ABS=0x3A
End-0.5*tCK: HC=0x03 ABS=0x38
Final: HC=0x03 ABS=0x3A
BYTE 6:
Start: HC=0x01 ABS=0x48
End: HC=0x03 ABS=0x58
Mean: HC=0x02 ABS=0x50
End-0.5*tCK: HC=0x02 ABS=0x58
Final: HC=0x02 ABS=0x58
BYTE 7:
Start: HC=0x01 ABS=0x54
End: HC=0x04 ABS=0x34
Mean: HC=0x03 ABS=0x04
End-0.5*tCK: HC=0x03 ABS=0x34
Final: HC=0x03 ABS=0x34

DQS calibration MMDC0 MPDGCTRL0 = 0x4338034C, MPDGCTRL1 = 0x03300328

DQS calibration MMDC1 MPDGCTRL0 = 0x033A0348, MPDGCTRL1 = 0x03340258

Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 00000001:byte 0 fail.
result 00000011:byte 0, 1 fail.

///// Question 2 ////

this resulte has 1 fail. Is that a problem? or not

///// Question 2 ////

Starting Read calibration...

ABS_OFFSET=0x00000000 result[00]=0x11111111
ABS_OFFSET=0x04040404 result[01]=0x11111111
ABS_OFFSET=0x08080808 result[02]=0x11111111
ABS_OFFSET=0x0C0C0C0C result[03]=0x11111111
ABS_OFFSET=0x10101010 result[04]=0x11111111
ABS_OFFSET=0x14141414 result[05]=0x11111111
ABS_OFFSET=0x18181818 result[06]=0x11111111
ABS_OFFSET=0x1C1C1C1C result[07]=0x11011001
ABS_OFFSET=0x20202020 result[08]=0x00011001
ABS_OFFSET=0x24242424 result[09]=0x00010000
ABS_OFFSET=0x28282828 result[0A]=0x00010000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00010000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000000
ABS_OFFSET=0x54545454 result[15]=0x00000100
ABS_OFFSET=0x58585858 result[16]=0x00000100
ABS_OFFSET=0x5C5C5C5C result[17]=0x00100110
ABS_OFFSET=0x60606060 result[18]=0x01100110
ABS_OFFSET=0x64646464 result[19]=0x01100110
ABS_OFFSET=0x68686868 result[1A]=0x11101111
ABS_OFFSET=0x6C6C6C6C result[1B]=0x11111111
ABS_OFFSET=0x70707070 result[1C]=0x11111111
ABS_OFFSET=0x74747474 result[1D]=0x11111111
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111

Byte 0: (0x24 - 0x64), middle value:0x44
Byte 1: (0x1c - 0x58), middle value:0x3a
Byte 2: (0x1c - 0x50), middle value:0x36
Byte 3: (0x24 - 0x64), middle value:0x44
Byte 4: (0x30 - 0x68), middle value:0x4c
Byte 5: (0x1c - 0x58), middle value:0x3a
Byte 6: (0x20 - 0x5c), middle value:0x3e
Byte 7: (0x20 - 0x64), middle value:0x42

MMDC0 MPRDDLCTL = 0x44363A44, MMDC1 MPRDDLCTL = 0x423E3A4C

Starting Write calibration...

ABS_OFFSET=0x00000000 result[00]=0x11111111
ABS_OFFSET=0x04040404 result[01]=0x11111111
ABS_OFFSET=0x08080808 result[02]=0x11111111
ABS_OFFSET=0x0C0C0C0C result[03]=0x10110111
ABS_OFFSET=0x10101010 result[04]=0x10110010
ABS_OFFSET=0x14141414 result[05]=0x10100010
ABS_OFFSET=0x18181818 result[06]=0x00100000
ABS_OFFSET=0x1C1C1C1C result[07]=0x00100000
ABS_OFFSET=0x20202020 result[08]=0x00100000
ABS_OFFSET=0x24242424 result[09]=0x00000000
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000000
ABS_OFFSET=0x54545454 result[15]=0x00000000
ABS_OFFSET=0x58585858 result[16]=0x00000000
ABS_OFFSET=0x5C5C5C5C result[17]=0x00000000
ABS_OFFSET=0x60606060 result[18]=0x00000000
ABS_OFFSET=0x64646464 result[19]=0x01000000
ABS_OFFSET=0x68686868 result[1A]=0x01001000
ABS_OFFSET=0x6C6C6C6C result[1B]=0x11011110
ABS_OFFSET=0x70707070 result[1C]=0x11011111
ABS_OFFSET=0x74747474 result[1D]=0x11011111
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111

Byte 0: (0x10 - 0x6c), middle value:0x3e
Byte 1: (0x18 - 0x68), middle value:0x40
Byte 2: (0x10 - 0x68), middle value:0x3c
Byte 3: (0x0c - 0x64), middle value:0x38
Byte 4: (0x14 - 0x68), middle value:0x3e
Byte 5: (0x24 - 0x74), middle value:0x4c
Byte 6: (0x0c - 0x60), middle value:0x36
Byte 7: (0x18 - 0x68), middle value:0x40

MMDC0 MPWRDLCTL = 0x383C403E,MMDC1 MPWRDLCTL = 0x40364C3E

MMDC registers updated from calibration

Write leveling calibration
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x0021001C
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x002B001E
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x00190023
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x000A001C

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x4338034C
MPDGCTRL1 PHY0 (0x021b0840) = 0x03300328
MPDGCTRL0 PHY1 (0x021b483c) = 0x033A0348
MPDGCTRL1 PHY1 (0x021b4840) = 0x03340258

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x44363A44
MPRDDLCTL PHY1 (0x021b4848) = 0x423E3A4C

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x383C403E
MPWRDLCTL PHY1 (0x021b4850) = 0x40364C3E

Success: DDR calibration completed!!!

///// Question 3 ////

DDR calibration was done. that means DDR operation is OK?

and I don't need to add action after ? or I need to act something?

and how to handle mass production.. let me know guide.

///// Question 3 ////

The DDR stress test can run with an incrementing frequency or at a static freq
To run at a static freq, simply set the start freq and end freq to the same value
Would do you want run DDR Stress Test? Type 'y' to run and 'n' to skip

Enter desired START freq (135 to 672 MHz), then hit enter.
Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.
533
The freq you entered was: 533

Enter desired END freq (135 to 672 MHz), then hit enter.
Make sure this is equal to or greater than start freq
533
The freq you entered was: 533

Do you want to run DDR Stress Test for simple loop or Over Night Test?
Type '0' for simple loop. Type '1' for Over Night Test

DDR Stress Test Iteration 1
Current Temperature: 41
============================================

DDR Freq: 532 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

DDR Stress Test is complete!

[pengyong_zhang]

Hi, @albatros74 

>>>I think that calibaration means all devices need to calibration and save for each device.

>>>calibration value is not fix device by device. isn't that right?

Each time you boot your board, the DDR will run the training. So, the calibration is used for test if your DDR is OK for your PCB board. No need run it to all of the same board.

B.R

[albatros74]

Thank you for your comment.

[pengyong_zhang · Accepted solution]

Hi, @albatros74 

Question 1 : You can found the MR1 define in JEDEC "JESD79-3F.pdf" document.

Question 2 : It is not a problem.

Question 3 : 

>>>DDR calibration was done. that means DDR operation is OK?

Yes , It is OK.

>>>and I don't need to add action after ? or I need to act something?

No need more action.

>>>and how to handle mass production.. let me know guide.

What do you mean mass production?

B.R

[albatros74]

Hi pengyong

Question 1 : You can found the MR1 define in JEDEC "JESD79-3F.pdf" document.

: I will check

Question 2 : It is not a problem.

: Thank you. ^^

>>>and how to handle mass production.. let me know guide.

What do you mean mass production?

: I think that calibaration means all devices need to calibration and save for each device.

 calibration value is not fix device by device. isn't that right?

so, if i will update calibration value each device. I think that it needs to too or test and save way in the factory.

BR