Cortex-M4 bare-metal application cannot read data from the shared memory(OCRAM)

[Bhargava]

Hi,

I am running Linux on Cotex-A53 and bare-metal application on Cotex-M4. The communication channel used between is shared memory i.e. OCRAM.

If M4 keeps sending or putting data at the OCRAM location the A53 can read all the data that is put by M4 whereas the other way round is not working as expected i.e., if A53 puts data continuously, from the M4 only first data is received and it is read only once, the subsequent read to that particular location results in the value that is read first, the updated data is not read.

Is this the issue at M4 side or A53 side?

Is A53 blocking access to OCRAM for M4?

From Linux application we are mapping OCRAM memory using mmap(). If mmap() is the problem then what are the alternatives to mmap?

If this is the Cache Coherence problem then how it can be resolved.

Kindly support for this issue.

Additional details:

SoC : iMX8M Mini

Shared memory: OCRAM (0x00910000)

Regards,

Bhargava

[Bhargava]

Hi Igor,

Thank you so much for sharing.

Disabling code bus cache did solve the issue.

Can I please know if disabling Processor Code bus cache affects the normal execution of the application?

Regards,

Bhargava

[igorpadykov]

Hi Bhargava

no, it does not affect the normal execution of the application.

Best regards
igor

[Bhargava]

Hi Igor,

Thanks for responding, it was indeed helpful.

Regards,

Bhargava

[igorpadykov · Accepted solution]

Hi Bhargava

  In M4 core address map, the OCRAM address 0x00900000 belongs to Processor Code bus ( 0x0000_0000 - 0x1FFF_FFFF) and the cache is enabled in LMEM controller.

  So we need to disable code bus cache and buffer in LMEM controller.

  Please try to modify function SystemInit() in system_MIMX8MM6_cm4.c as below:

// TY comments to disable code bus cache. {
//LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
//LMEM->PCCCR |= LMEM_PCCCR_GO_MASK;
/* Wait until the command completes */
//while (LMEM->PCCCR & LMEM_PCCCR_GO_MASK) {
//}
/* Enable cache, enable write buffer */
//LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
// } TY comments to disable code bus cache.

Best regards
igor