Configuring iATU on i.MX6

[gasperkorinsek]

Hello,

We're using i.MX6Q Linux 3.10.17_1.0.0_ga on SabreSD board, configured as PCIe RC.

Attached propiatery EP device on PCIe has three 32-bit BARs, 1MBytes each. Registers of interest on EP go from address 0x01000000 on.

On i.MX6 Linux performs the following BAR mapping:

32-bit BAR0 - 1MByte: 0x01200000 - 0x12FFFFF

32-bit BAR1 - 1MByte: 0x01300000 - 0x13FFFFF

32-bit BAR2 - 1MByte: 0x01300000 - 0x13FFFFF

Without using iATU we can only access registers on EP from address 0x01200000 on.

We've tried enabling iATU in file drivers/pci/host/pci-imx6.c as described below, but the address translation didn't work (we've got the same register content as prior enabling iATU)

writel(0, pp->dbi_base + PCIE_ATU_VIEWPORT);

writel(0x01000000, pp->dbi_base + PCIE_ATU_LOWER_BASE);

writel(0x00000000, pp->dbi_base + PCIE_ATU_UPPER_BASE);

writel(0x010fffff, pp->dbi_base + PCIE_ATU_LIMIT);

writel(0x00200000, pp->dbi_base + PCIE_ATU_LOWER_TARGET);

writel(0x00000000, pp->dbi_base + PCIE_ATU_UPPER_TARGET);

writel(PCIE_ATU_TYPE_MEM, pp->dbi_base + PCIE_ATU_CR1);

writel(PCIE_ATU_ENABLE, pp->dbi_base + PCIE_ATU_CR2);

I would appreciate any suggestions or ideas how to make iATU operational to access registers on EP from 0x01000000 on.

Best regards,

[gasperkorinsek · Accepted solution]

Solution is described below (base/target addresses were incorrect - reference manual a bit misleading)

#define BAR0_ADDR 0x01200000

#define VTSS_ADDR 0x01000000

writel(2, pp->dbi_base + PCIE_ATU_VIEWPORT); // 0 and 1 are already used in pcie-designware.c

writel(BAR0_ADDR, pp->dbi_base + PCIE_ATU_LOWER_BASE);

writel(0, pp->dbi_base + PCIE_ATU_UPPER_BASE);

writel(BAR0_ADDR + SZ_1M - 1, pp->dbi_base + PCIE_ATU_LIMIT);

writel(VTSS_ADDR, pp->dbi_base + PCIE_ATU_LOWER_TARGET);

writel(0, pp->dbi_base + PCIE_ATU_UPPER_TARGET);

writel(PCIE_ATU_TYPE_MEM, pp->dbi_base + PCIE_ATU_CR1);

writel(PCIE_ATU_ENABLE, pp->dbi_base + PCIE_ATU_CR2);