Changes in UART2 pad setting for u-boot

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Changes in UART2 pad setting for u-boot

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piyushashtikar
Contributor II

We are planning to switch from LTIB Platform to Yocto to build images for our custom board based on sabrelite,

using u-boot-boundary.

Uart debug console in our board is UART2,same as that in sabrelite.
However, Uart signals are mapped to PAD_GPIO7 and PAD_GPIO8 instead of default EIM_D26 & EIM_D27.

Now, we have done this precisely in LTIB and know the exact working procedure according to LTIB documentation.

But in Yocto we are not able to see debug console output,regarding this i have a doubt.



We build core-image-base and tried u-boot-boundary and did setting like this in
mx6qabrelite.c
iomux_v3_cfg_t const uart2_pads[] = {
    //MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
    //MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
    MX6_PAD_GPIO_7__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
    MX6_PAD_GPIO_8__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};


Do we have to do any other setting for uboot so that we get output on debug uart 2?

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Yuri
NXP Employee
NXP Employee

  According to description of Pad Mux Register IOMUXC_SW_MUX_CTL_PAD_GPIO08

to configure it as UART2_RX_DATA (ALT4 mode) it is required additionally
to configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode ALT4.


Have a great day,
Yuri

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547 Views
Yuri
NXP Employee
NXP Employee

  According to description of Pad Mux Register IOMUXC_SW_MUX_CTL_PAD_GPIO08

to configure it as UART2_RX_DATA (ALT4 mode) it is required additionally
to configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode ALT4.


Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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