Hello Friends,
I am using imx28evk running linux kernel 3.10.29. I have found that the SSP0 (MMC slot 0) can only run maximum of clock 28.8MHz as mentioned in the
file: drivers/mmc/host/mxs-mmc.c
Line#666
mmc->f_min = 400000;
mmc->f_max = 288000000;
I want to plug the TI wifi module that runs on 50MHz. In this case, I would like to increase the clock frequency of SSP0 to 50 MHz. Is there any way I can change it?
Moreover, I found that "ref_io0" is set to 288 MHz below from file: drivers/clk/mxs/clk-imx28.c. Which code changes the frequency from 228 MHz to 28.8 MHz (maximum) ?
/*
118 * 480 MHz seems too high to be ssp clock source directly,
119 * so set frac0 to get a 288 MHz ref_io0 and ref_io1.
120 */
121 val = readl_relaxed(FRAC0);
122 val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
123 val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
124 writel_relaxed(val, FRAC0);
Any help is highly appreciated.
Thank you,
Ankur
已解决! 转到解答。
Hello Floks,
Found the Solution:
I just edited drivers/clk/mxs/clk-imx28.c and now the ssp0_div and ssp0 clock goes to 288 MHz.
Below are the additions to function clk_misc_init(void):
val = readl_relaxed(SSP0);
printk("Before Change ctrlssp0 0x%x\n",val);
val = val & ~0x17;
val = val | 0x1;
writel_relaxed(val, SSP0);
val = readl_relaxed(SSP0);
printk("After Change: ctrlssp0 0x%x\n",val);
Thanks all for support.
Have a Good One,
Ankur
Hello Folks,
I got to know from the clock Hierarchy that ref_io0 is 288 MHz and the register values is also correct. But I don't able to know how the SSP0_DIV clock goes down to 57.6 MHz, I am sure that register affects it as the divider value is 5.
Kernel: 3.10.29
root@imx28evk:~# cat /sys/kernel/debug/clk/clk_summary
ssp0_sel 1 1 288000000
ssp0_div 1 1 57600000
ssp0 1 1 57600000
I tried looking into drivers/clk/mxs/clk-imx28.c and drivers/clk/mxs/clk-div.c but didnt get any clue about how HW_CLKCTRL_SSP0 register gets divider value 5. Any hint will be appreciated.
Thank you,
Ankur
Hello Floks,
Found the Solution:
I just edited drivers/clk/mxs/clk-imx28.c and now the ssp0_div and ssp0 clock goes to 288 MHz.
Below are the additions to function clk_misc_init(void):
val = readl_relaxed(SSP0);
printk("Before Change ctrlssp0 0x%x\n",val);
val = val & ~0x17;
val = val | 0x1;
writel_relaxed(val, SSP0);
val = readl_relaxed(SSP0);
printk("After Change: ctrlssp0 0x%x\n",val);
Thanks all for support.
Have a Good One,
Ankur