I'm working on a rail-based system built from multiple i.MX RT1064 devices, where a PTP master is used to synchronise with multiple PTP slaves. However, in scenarios where the PTP master does not have continuous access to a high quality external time (e.g. NTP, GPS),I would like the PTP master's 1588 time to be synchronised with the 32.768KHz RTC XTAL instead.
The code I'm working with uses a 25MHz internal clock (i.e. the 1588 counter steps up by 40 nanosecs each tick), but I believe that this 25MHz internal clock is synthesised from the 24MHz XTAL driving the main processor clock, not from the 32.768KHz RTC XTAL.
The RT1064 manual mentions that the processor synthesises a (lower-quality) 24MHz internal clock from an external 32.768KHz RTC_XTAL (to be used if the 'real' 24MHz external XTAL is absent, e.g. OSC_SEL / RC_OSC_EN etc), but I can't see this mentioned in any of the clock tree diagrams.
I do understand that I could use the synthetic 24MHz internal clock to drive all the PLLs etc (albeit less reliably), but I actually only want to use it to drive the 1588 clock.
Hence I'm wondering: is the 24MHz internal clock synthesised from the external 32.768KHz clock available anywhere in the clock tree? I think this would be a much better 'raw' 1588 clock source for a PTP master to use.
Dear @np
Thanks a lot for being so patient on this ticket.
I am now handling this case and I would like to ask for you some more time to have an accurate answer to your issue by doing some tests and double-reviewing.
Appreciating so much your patience, I will look forward and then get back to you with a feedback. Thanks a lot!
Best Regards.
Pablo Avalos.
Note: some clocks are derived from this RC 24MHz clock via a 1MHz intermediate clock, e.g. ewm_lpo_clk_0, wdog3_ext_clk.
If I'm not using any of these outputs or any low power modes, could I perhaps instead synthesise a 25MHz clock (via COUNT_RC_TRG) and then not divide that down at all (via COUNT_1M_TRG) and use ewm_lpo_clk_0 (kCLOCK_Ewm0 on CCGR3) or wdog3_ext_clk (kCLOCK_Wdog3 on CCGR5) to drive the 1588 clock?
Failing that, could I synthesise a 20MHz clock (via COUNT_RC_TRG) and then divide that by 1 (via COUNT_1M_TRG)?