Hi NXP
Our customer application is camera display in i.MX8M.
He try to connect ov2749(imx8 RGB888 format to BT1122 format to FPGA to camera).
Then He run "camerawidgetexample" in Linux.
The camera video will be play 2~3 second, then video will hung up (not any change).
Then customer will be get fail message:
mx6s-csi 30b80000.csi2_bridge: mx6s_csi_irq_handler Rx fifo overflow
The customer guess the issue is mipi setting issue.
Do you have any idea will be fixed the issue?
what imx8m do you use? imx8mm or imx8mq
and what bsp version do you use? did you change the csi driver? like mx6s_capture.c?
what format do the imx8m get? rgb888, right?
HI
BSP : 4.14.98
iMX8MQ
The format is RGB888.
We will get error msg as below:
mx6s-csi 30b80000.csi2_bridge: mx6s_csi_irq_handler Rx fifo overflow
We found there is the same issue
Any suggestion?
Thanks
as I known, i.mx8m doesn't support rgb888 in the default bsp, how did you change the source code to support rgb888?
as I known, To support 720P60 RGB888 MIPI camera on L4.14.78, configure CSICR18. PARALLEL24_EN=1, and CSICR3.TWO_8BIT_SENSOR=0. did you set them correctly?
besides of this, for the csi fifo errata, from the development team:
Title: MIPI CSI: Receive FIFO Overflow may lead to system hang
Errata Description:
When receive FIFO data in MIPI CSI can not be written to memory in time if the system is heavily loaded with DDR memory requests, overflow will happen. It may lead to illegal AHB bus access at CSI AHB master port and then causes system hang.
Note that the possibility of MIPI CSI1 overflow will be lower than MIPI CSI2. MIPI CSI1 can support 4 outstanding write transition, however MIPI CSI2 can support 2 outstanding write transition. So MIPI CSI1 will realize more memory bandwidth.
Errata Workaround
The recommended workaround for this erratum is to avoid MIPI CSI overflow happen. Two undocumented debug registers can be used to monitor CSI FIFO levels in real time. When FIFO reaches one threshold, disable CSI and restart CSI.
For example, create one program on M4 core to monitor CSI FIFO level and do as follows:
Hi @joanxie,
I am facing similar problems and i have some questions regarding the recommended workaround.
1) In step 2 i should write 0xff to CSI_PHY_CTL_REG (0x30A7_0104) to restart the CSI. Does this really restart the csi? From the documentation i read that the lower 4 bit of register 0x30A7_0104 can be used to disable the data lanes 0-3. the rest of the register is reserved. does setting bit 4 to 7 to 1 have some effect?
2) If the CSI lanes are disabled in step 2, when do they get enabled again? Is there a defined/recommended procedure?
3) Does the application also have to handle such restarts triggered from the M4? e.g close and open v4l2?
4) Does NXP offers an example for the M4 monitor program?
BR rabe