Hi Freescale,
I am trying to use the CCAM_ANALOG_MISC2:AUDIO_DIV_MSB, AUDIO_DIV_LSB so I can divide the PLL4_AUDIO clock (pll4_main_clock) from 688.128MHz to 86.016MHz. I can verify the PLL4_AUDIO is reaching to 688.128MHz when using CCM_ANALOG_PLL_AUDIOn:DIV_SELECT=28, CCM_ANALOG_PLL_AUDIO_NUM=672, CCM_ANALOG_PLL_AUDIO_DENOM=1000. This is following equation with Fref=24MHz:
I can also verify the CCM_ANALOG_PLL_AUDIOn:POST_DIV_SELECT=0 (divide by 4) is working to give a pll4_main_clock=172.032MHz. However, when trying to configure CCM_ANALOG_MISC2:AUDIO_DIV_MSB & AUDIO_DIV_LSB to divide by 2:
I do not see the pll4_main_clock=86.016MHz.
My observation is using CCM_CCOSR:CCM_CLKO1 to use PLL4_MAIN_CLK as the source clock with a divider by 1.
I also took note in CCM_ANALOG_MISC2:AUDIO_DIV_MSB where the: output clock of the audio PLL should be "gated" prior to changing this divider to prevent glitches. However when configuring CCM_ANALOG_PLL_AUDIOn:POWERDOWN=1 during ENABLED=1/BYPASS=1, I am unable to get the PLL to enter a DEACTIVE HIGH STATE, which should make the PLL "gated".
I tried with with CCM_ANALOG_PLL_VIDEO and that seems to be working fine.
My order for switching PLL speeds at reset:
1. BYPASS = 0 --> (POWERDOWN will remain = 1 & ENABLE will be = 0)
2. CONFIGURE PLL DIV_SELECT, NUMERATOR, DENOMINATOR, MISC2
3. ENABLE = 1
4. POWERDOWN = 0
5. WAIT WHILE CCM_ANALOG_PLL_AUDIO:LOCK = 1
Is there anything else that I am missing when trying to "gate" PLL4_AUDIO? Or is PLL4_AUDIO is unable to be "gated" since there is no CCGR for pll4_main_clk?
Thanks in advance.
Chris.
