Hello everyone,
I'm new here,could you give me a few pointers with LPDDR2 SDRAM porting.
In my project, it's base on i.mx7ulp and the original Yocto BSP is set for LPDDR3.
Now I want to change the LPDDR3 to LPDDR2(1G) for my project's design, I already use the LPDDR2_RegisterProgrammingAid_V0_2.xlsx to create LPDDR2 relate setting register parameter in RealView.inc file.
According to "I.MX BSP Porting Guide " I already do some edit but I still have some question as below :
1. Whether I only need according to the register setting sequence and value in RealView.inc fill all parameter into the "imximage.cfg file" and then rebuild : bitbake -f -c compile u-boot-imx ?
Is there any files need to modify for porting SDRAM form LPDDR3 change to LPDDR2 ?
2. If the register setting sequence in imximage.cfg file is not match RealView.inc file , it will lead to an error or not?
3. Does the mx7ulp_evk.h file need to modify?
4.The //PCC0 ,//PCC1 and //PCC2 relate register setting in "RealView.inc file" are all set to value: 0x40000000 , whether I don't need fill these setting into imximage.cfg file?
5. The plugin.S file in git/board/freescale/mx7ulp_evk need to modify or not ? Does this file will be used when u-boot in boot phase?
Thank~
Dear igorpadykov
Can I ask you to do me a favour? I already fill in LPDDR2 parameters into "imximage.cfg" refer to "linux/board/freescale/mx7ulp_arm2 imximage_lpddr2.cfg" as you mentioned previously, but now I face another problem is the u-boot stuck and it doesn't show any message at UART port on my_customer board during boot stage.
Because my_customer board is boot from uSD-Card, so I measured both "CLK" and "DATA0" signals on uSD-card to confirm u-boot process is fail.
I find that "CLK" and "DATA0" signals will continue normal active on NXP-EVB during boot stage (fig 1.) ,but both these two signal on my_ customer board only active at the beginning during boot stage and then will STOP (fig 2.) .
fig 1 . Red : DATA0 Green: CKL on NXP -EVB during boot stage.
fig 2 . Red : DATA0 Green: CKL on MY- Board during boot stage.
these are what I modified in BSP as below :
1. change setting in "mx7ulp_evk.c" uart port to match my_customer board design.
2. imx7ulp.dtsi(in U-boot) (for match my_customer design)
3. imx7ulp-evk.dts(in U-boot) (for match my_customer design)
4. imximage.cfg.
5. And I re-build "bitbake u-boot-imx" with no error.
My question is shown as below :
1. Actually ,relate to porting DDR process in the "i.MX BSP Porting Guide" only mention in chapter "3.2.1 Changing the DCD table for i.MX DDR initialization " , it's just indicate that we need to modify my_board.cfg.
I really want to known is HOW should I do to fill in DCD table parameters refer to RealView.inc ?
Is these any document can show more detail about modify the DCD table?
2. Whether the modified of device tree in u-boot source file will cause a u-boot fail?
( The modified "u-boot-imx" image doesn't show any error message when I re-build it . )
3. According to fig 2. wave form ,could you give me some tips about this case ? Is the DCD table configuration mistake cause this case ?or device tree configuration mistake in u-boot source code?
Thanks.
Hi Sam
example of lpddr2 configuration can be found in
linux/board/freescale/mx7ulp_arm2 imximage_lpddr2.cfg
https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/mx7ulp_arm2?h=imx_v2017.03...
plugin.S file is not needed if plugin mode is not used (more description can be found in Boot
Chapter of Reference Manual).
>Does the mx7ulp_evk.h file need to modify?
no
>Is there any files need to modify for porting SDRAM form LPDDR3 change to LPDDR2 ?
except *.cfg file, in linux/arch/arm/mach-imx there are specific for memory low power codes
https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm/mach-imx?h=imx_4.9.88_2.0.0_ga
Best regards
igor
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Dear igorpadykov
Thanks for your help, you do gave me a big favor.