Hi
I have a system in which I detect RAM by writing and reading till I get an error . To test this I set the MMDC0_MDASP for cs0 to a value less than the total ram on board. The system hangs on the access. or possibly goes to an unpredicatable abort. It is fine if it gets past the actual installed ram however. I preset the data abort vector to a custom routine, but it doesn't behave properly. It looks like the controller is retrying the address, producing repeated aborts.
I have checked that the routines on the vector behave correctly by doing a LDR from the top of PCIe space, which aborts predictably.
Can anyone shed any light on this?
Hi Yuri
Yes I know about this.. The 'complaint' or 'observation' is that in this circumstance - accessing DDR address beyond the limit of CS0 addressing - appears to cause a repeated data abort .. the abort vector is being re invoked, though the code flow does not reattempt a read. .. is this in anyway expected? .. I add that I have tested and retested the code.. If I cause a data abort by doing a LDR in PCIe space the flow of code is followed as expected. If I do exactly the same, but beyond the end address specified in MMDC0_MDASP, then there seems to be a repeated attempt to read the space, and hence repeated data abort,
The link register (with a –8 adjustment), gives the address of the instruction executing before the abort exception,
therefore, if return address is LR + 8, abort event gets reproducable.