At the timing of the interruption power-off to power-on, there when the voltage of the part of the power supply does not fall, There is some problem?
Please refer attachment Fig.
The specification VDD_SNVS_IN after the other power supply on.
As shown in attachment Figure widened voltage of 1.8 v and 3.3 v systems in the VDD_SNVS_IN injection timing.
Is this problem?
How voltage down of 1.8v and 3.3v ?
Also Is there such threshold of spec?
已解决! 转到解答。
The residual voltage, strictly speaking, can violate recommended power up
sequence ; in particular - the restriction that GPIO pins must not be under
external voltages. So, please do not use relatively quick power off / on sequence
to prevent effect of residual voltage on capacitors.
As for the case, shown on the "Power_on_timing" figure, we can see a violation, since
VDD_SNVS_IN supply must be turned on before any other power supply, assuming
other power suppliers start their rising from zero voltage.
Have a great day,
Yuri
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The residual voltage, strictly speaking, can violate recommended power up
sequence ; in particular - the restriction that GPIO pins must not be under
external voltages. So, please do not use relatively quick power off / on sequence
to prevent effect of residual voltage on capacitors.
As for the case, shown on the "Power_on_timing" figure, we can see a violation, since
VDD_SNVS_IN supply must be turned on before any other power supply, assuming
other power suppliers start their rising from zero voltage.
Have a great day,
Yuri
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
Hi ,
Yuri
Thank you for your replay.
Add the discharge resistors, as far as possible until the 0 V power down protection.
But remains of 100 mV of 3.3 V for GPIO.
We anticipate no problems voltage is actually the concern you have??
Would you Please also check .
The i.MX6 specs do not require voltage rising from 0.0 V, in this sense the 100 mV
does not look as a violation. But to be fully on safe side it may be recommended
to apply an external POR signal (to avoid using internal one, based of voltage ramp)
~Yuri.