About burst transfer of SDMA in i.MX6DQ.

[keitanagashima]

Dear Sir or Madam,

Hello.

I have a question about burst transfer of SDMA in i.MX6DQ.

Refer to 22.5.8 AXI (Master) Bus Cycles Support in i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 1, 04/2013.

There are below descriptions.

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Only 32-bit word size accesses are supported for burst

mode accesses.

Only 8-bit (1 byte), 16-bit (2 byte) and 32-bit (4 byte) word

size supported for single access.

Maximum number of burst length is 16.

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=About DMA burst transfer=

When the burst accesses with following use case, is it supported except 32 bits word size access, too?

[Case.1]

Source : LPDDR2

Destination : EIM

[Case.2]

Source : EIM

Destination : LPDDR2

Keita

[Yuri · Accepted solution]

> When the burst accesses with following use case, is it supported except 32 bits word size access, too?

No. Only 32-bit aligned accesses should be used for WEIM bursts. 

[keitanagashima]

Do anyone have some update?

Keita