About Full HD size preview in i.MX6DQ.

[keitanagashima]

Dear All,

Hello. I have question about Full HD size preview in i.MX6DQ.

We want to achieve the below thing.

External Camera --> [1080p@60(YUV422)] --> MIPI-CSI2 --> Output 1080p@60fps via HDMI.

*YUV422 = 16bpp

Can either of the following two ways be achieved the function of preview with 1080p@60?

Case.1) Change into RGB24 in IC(Image Converter) of IPU.

Case.2) Output YUV422 just as it is in HDMI.

Best Regards,

Keita

[weidong_sun]

Hi Keita,

   The MAX speed of  MIPI CSI-2 on i.MX6 is 3.2Gbps, 1080P@60 & 24 bpp is 148.5 * 24 = 3.564Gbps, so if you want to use MIPI to capture 1080P@60, MIPI can't normally work.

Regards,

Weidong

[keitanagashima]

Dear Weidong,

Hello.

We will use MIPI-CSI2 with 4lanes (400 Mbyte/Sec).

And 1080p@60 & yuv422 is "1980 * 1080 * 60[fps] * 1.35 * 16[bit] = 320.4 [Mbyte/sec]"

Limitation : 400 [Mbyte/Sec] > 320.4 [Mbyte/sec]

Best Regards,

Keita

[gusarambula]

weidong.sun​, would you please help us following up Keita Nagashima's comment?

I think the 800Mbps/lane in 4-lane mode still stands, which would be the 3.2Gbps limitation you're mentioning.However, your calculation accounts for 24 bpp and Keit Nagashima's accounts for 16bpp. Would it be possible to implement the later configuration?

[weidong_sun]

ok, Keita,

    got it !, I think your application should be ok, because MIPI clock < 3.2Gbps , mipi can normally work.

Regards,

weidong

[keitanagashima]

Dear Weidong,

Thank you for your reply.

I think that camera input is no problem.

But, I worried about whether or not the following below cases is concluded.

====

Case.1) Change into RGB24 in IC(Image Converter) of IPU.

Case.2) Output YUV422 just as it is in HDMI.

====

I think that Case.2 is no problem, because  it can fly-by processing.

But, I don't know about Case.1.

Best Regards,

Keita

[weidong_sun · Accepted solution]

Hi keita,

     YUV422 format can be displayed by IPU, don't need to convert it to RGB format, so your ' case 1' is no problem.

Regards,

Weidong

[Danube]

Hi Weidong,

Base on i.MX6 RM file ,

IPU receives 2 components per cycle from the MIPI-CSI2 interface

• The maximum speed of the interface is:

• 200Mhz for 4 data lanes configuration

• 250Mhz for 2 data lanes configuration

• 200Mhz for 4 data lanes configuration (800Mbps/lane, 400MByte/sec)

• 187.5Mhz for 3 data lanes configuration (1000Mbps/lane, 375MByte/sec)

• 125Mhz for 2 data lanes configuration (1000Mbps/lane, 250MByte/sec )

• 62.5Mhz for 1 data lane configuration (1000Mbps/lane, 125Mbyte/sec)

Is 125MHz for 2 data lanes is not correct ?
We think 4 lanes total BW is 3.2Gbps , so MIPI clock max value  is 400MHz , Right ?

2 lance total BW is 2.0G bps , so MIPI clock max value is 500MHz , Right ?

[keitanagashima]

Hi Weidong,

Thank you for your reply.

OK. I got it.

Best Regards,

Keita