as another alternative one can consider LVDSCLK1 (CCM_CLK1_N, CCM_CLK1_P balls)
described in sect.18.7.18 Miscellaneous Register 1 (CCM_ANALOG_MISC1n) i.MX6ULL Reference Manual
https://www.nxp.com/webapp/Download?colCode=IMX6ULLRM
But I didn't see any clock divider option on a sec.18.7.18 for 8MHz clock out from 24MHz.
Hi prabhu
one can try to output AUDIO_PLL (reprogram it to necessary frequency
using CCM_ANALOG_PLL_AUDIOn register) and dividers in AUDIO_DIV_LSB(MSB)
CCM_ANALOG_MISC2n.
Other alternatives may be try to use PWM, EPIT or GPT modules for such purpose.
GitHub - sasamy/imx-snd-pwm: A simple sound card based on PWM for i.mx6x processors
Best regards
igor
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