how many boards have this issue?
please check the signal integrity of MCLK.
is there a cap. connected in between clock and ground? what is the value?
if possible, could you send me the schematic of wm8962 part of your board?
几乎每块板子都会有这个问题。
MCLK用示波器看了是24MHz,波形还算好,但是没有眼图测试仪器。
部分原理图如下:
Hello Hertz,
2 suggestions for your debugging the part.
(1) clock source code
In "linux/drivers/clk/imx/clk-imx6q.c "
/* * Let's initially set up CLKO with OSC24M, since
this configuration * is widely used by imx6q board designs to clock audio
codec. */
...
imx_clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
imx_clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
clk_set_rate(clk[IMX6QDL_CLK_CKO], 24000000); // add this line, please!
...
Then power on board, test audio.
(2) Remove R266 & Populate "Y3/R268/C279/C280" (断开 U23,把24MHz晶体焊上去)
Then power on board, test audio.
【Note】
I feel there are some issues with U23, so do above test, please!
Have a nice day.