[i.MX8/8X/8M]Force PCIE to work at GEN1/2 mode

[#1]

Customer can force PCIE to work at GEN1/GEN2 mode if PCB layout is not good.

Pls refer to:

linux/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt:40:- fsl,max-link-speed: Specify PCI gen for link capability. Must be '2' for

i.MX8M:

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi

index f4dcf7ac3c98..262db6f93cb2 100755

--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi

+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi

@@ -1314,7 +1314,7 @@

                    <&clk IMX8MQ_CLK_PCIE1_AUX>,

                    <&clk IMX8MQ_CLK_PCIE1_PHY>;

             clock-names = "pcie", "pcie_bus", "pcie_phy";

-            fsl,max-link-speed = <2>;

+            fsl,max-link-speed = <1>;

             ctrl-id = <0>;

             power-domains = <&pcie0_pd>;

             status = "disabled";

@@ -1344,7 +1344,7 @@

                    <&clk IMX8MQ_CLK_PCIE2_AUX>,

                    <&clk IMX8MQ_CLK_PCIE2_PHY>;

             clock-names = "pcie", "pcie_bus", "pcie_phy";

-            fsl,max-link-speed = <2>;

+            fsl,max-link-speed = <1>;

             ctrl-id = <1>;

             power-domains = <&pcie1_pd>;

             status = "disabled";

diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c

index 54459b52f526..a63de7e7bae0 100644

--- a/drivers/pci/dwc/pci-imx6.c

+++ b/drivers/pci/dwc/pci-imx6.c

@@ -1548,6 +1548,7 @@ static int imx_pcie_establish_link(struct imx_pcie *imx_pcie)

      u32 tmp;

      int ret;

+    dw_pcie_dbi_ro_wr_en(pci);

      /*

       * Force Gen1 operation when starting the link.  In case the link is

       * started in Gen2 mode, there is a possibility the devices on the

i.MX8/8x:

fsl-imx8dx.dtsi

pcieb: pcie@0x5f010000 {

              /*

              * pcieb phyx1 lane1 in default, adjust it refer to the

              * exact hw design.

              */

.

.

.

.

.

              power-domains = <&pd_pcie>;

              fsl,max-link-speed = <1>;         /* 3=gen3, 1=gen1 */

              hsio-cfg = <PCIEAX2PCIEBX1>;

              hsio = <&hsio>;

              ctrl-id = <1>; /* pcieb */

              cpu-base-addr = <0x80000000>;

              status = "disabled";

       };

pci-imx6.c

@@ -1799,6 +1799,7 @@ static int imx_pcie_establish_link(struct imx6_pcie *imx6_pcie)

     u32 tmp;

     int ret;

+    dw_pcie_dbi_ro_wr_en(pci);

     /*

      * Force Gen1 operation when starting the link.  In case the link is

      * started in Gen2 mode, there is a possibility the devices on the

@@ -1870,11 +1871,13 @@ static int imx_pcie_establish_link(struct imx6_pcie *imx6_pcie)

            dev_info(dev, "Link: Gen2 disabled\n");

     }

+    dw_pcie_dbi_ro_wr_dis(pci);

     tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);

     dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);

     return 0;

 err_reset_phy:

+    dw_pcie_dbi_ro_wr_dis(pci);

     dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",

            dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),

            dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));