Introduction
ARM SoC+FPGA/CPLD is widely used in some application like industry control and data acquisition system, there were many customers adopted i.MX6 EIM (a memory parallel interface) to access FPGA/CPLD, and archived good data throughput, but EIM is removed from i.MX8M and i.MX9, some customers is asking for such a compatible solution for i.MX8/8M and coming i.MX9 family. FlexSPI is designed for connecting storage devices like NOR Flash, integrated in most of i.MXRT/i.MX8/LS products and provides flexible configuration for 4-wire/8wire working mode, this article provides a low-cost and efficiency demo to show how to support CPLD/FPGA via FlexSPI, as a replacement of EIM for EP i.MX8/9/LS products.
key features
- Implement a new kernel driver for FlexSPI to support read/write access to FPGA/CPLD.
- Support two type connections: Support 4-wire(QSPI) and 8-wire(HypeBUS, OctalSPI)
Deliverables
- A new kernel driver for FlexSPI to support read/write access to FPGA/CPLD by AHB command
- A kernel patch to disable the QSPI Flash in kernel
- A test program shows how to do read/write performance test.
Hardware
Hardware Prepare:
i.MX8MM-LPDDR4-EVK
Lattice LFE5U EVK
Figure1 4-wire SPI HW Block diagram
Figure2 8-wire OctalSPI
Hardware Rework on i.MX8MM-EVK
1 Need to remove the SPI-Flash(U5, MT25QU256ABA) on the i.MX8MM-EVK board, and wire below signals:
QSPI_DATA0
QSPI_DATA1
QSPI_DATA2
QSPI_DATA3
QSPI_SCLK
QSPI_nSS0
VDD_1V8
GND
Figure3 QPSI signals for FPGA/CPLD
Figure4 Hardware rework on i.MX8MM-EVK board
Note that, i.MX8MM-EVK QSPI power rails is 1.8v, so be careful that the FPGA/CPLD side IO should be 1.8V.
Software
BSP version
1 Linux BSP version: L5.10.52
Software Change
- Apply 0001-FlexSPI-FPGA-need-to-disable-flexspi-for-fpga-usage.patch in Linux kernel and generate the new dtb
- extract the flexspi-fpga driver
- compile the flexspi-fpga driver with the kernel$
$make -C $(YOUR_KDIR) M=$(FlexSPI_FPGAW_DIVER_DIR) modules ARCH=arm64 CROSS_COMPILE=$(CROSS_COMPILE)Deployment
- upload new generated i.mx8mm-evk.dtb to the target board(the 1st partition)
- upload the flex-spi driver and fpga/cpld test program to the target board
Test
Test1: Set the flexspi working at 40Mhz
$insmod imx_flexspi_fpga.ko pre_div=2 post_div=5
Read/write FPGA/CPLD test
.$/flexspi_fpga_test -p 0x08000000 -s 768Test2: Set the FlexSPI working at 100MHz
$ insmod imx_flexspi_fpga.ko pre_div=1 post_div=4Read/write FPGA/CPLD test
$./flexspi_fpga_test -p 0x08000000 -s 768
Limitation
- FPGA and Flash devices can’t work at the same time due to just one FlexSPI controller.
- Due to the IO assignment conflict in i.MX8M EVK design, this demo just tested 4-wire（QSPI) mode at 50MHz and got data throughput as expected.
Disclaimer:
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