Add i.MX93 LVDS driver in uboot

[#1]

Introduction

Platform: i.MX93 EVK

Uboot: origin/lf_v2022.04(lf-6.1.1-1.0.0)

The LVDS design and media block control in i.MX93 is very similiar with i.MX8MPlus.This article implements the LVDS driver in uboot.

You need apply 0001-Add-fake-adp5585-pwm-driver.patch which implements the adp5585 pwm driver in uboot. This is a fake pwm driver only implement the pwm driver framework. You can't use pwm value to adjust brightness for the moment, but this is enough to enable the backlight.

Then please apply 0002-Add-imx93-lvds-and-panel-driver.patch, you will see nxp logo with this panel:

https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/dy1212w-4856:DY...

Porting suggestions

1. Modify panel timing in drivers/video/simple_panel.c

/* define your panel timing here and
 * copy it in simple_panel_get_display_timing */
static const struct display_timing boe_ev121wxm_n10_1850_timing = {
	.pixelclock.typ		= 71143000,
	.hactive.typ		= 1280,
	.hfront_porch.typ	= 32,
	.hback_porch.typ	= 80,
	.hsync_len.typ		= 48,
	.vactive.typ		= 800,
	.vfront_porch.typ	= 6,
	.vback_porch.typ	= 14,
	.vsync_len.typ		= 3,
};

static int simple_panel_get_display_timing(struct udevice *dev,
					    struct display_timing *timings)
{
	memcpy(timings, &boe_ev121wxm_n10_1850_timing, sizeof(*timings));

	return 0;
}

2.Modify VIDEO_PLL

The VIDEO_PLL = pixel clock * 7. For default panel, the pixel clock is 71.143MHz and VIDEO_PLL  is 498MHz.

static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
	FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */
	FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */
	FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */
	FRAC_PLL_RATE(498000000U, 1, 166, 8, 0, 1),/* rate, rdiv, mfi, odiv, mfn, mfd */
	FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1),
	FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1),
	FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
	FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
	FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1),
};

3. Modify lcdif node in dts

<498000000>, <71142857>, <400000000>, <133333333>;

<VIDEO PLL>,<PIX CLK>, <MEDIA_AXI>,<MEDIA_APB>

 &lcdif {
 	status = "okay";
-	assigned-clock-rates = <484000000>, <121000000>, <400000000>, <133333333>;
+	assigned-clock-rates = <498000000>, <71142857>, <400000000>, <133333333>;
 };