Vybrid LPDDR2 Configuration

[ericaverill]

Hi,

We're using a Winbond W97AH6KBVX2I TR device in our product along with a Vybrid MVF51NN151. I'm attempting to update a LPDDR2 configuration file provided to us by Freescale and am running into some issues related to undocumented registers:

1. We currently have CR110 set to 0x00002020. The reference manual states that for LPDDR2 bits 16:0 have no meaning and should be set to 0, the reset default. When I try this setting our PHY calibration routine fails and the system does not boot correctly. Do these bits have some effect with LPDDR2? It would seem so.

2. We have additional registers, CR38, CR39, CR41, CR125, and CR131 which are labeled in the reference manual as reserved read-only but are being written in the code we were provided. If I remove these writes the memory no longer gets initialized correctly and the system won't boot.

I'm attempting to optimize memory timing as well as perform a general review to ensure that we are configuring the memory and memory controller correctly. Can you provide guidance on these registers?

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[TheAdmiral]

Hi Eric,

After reviewing the Vybrid Refernce Manual update, I see that there are a couple of mistakes. The following two fields do apply to LPDDR2 and need to be set with correct delay settings:

CR105[23:8]

CR110[15:0]

The Read Leveling parameters are required to correctly offset the DQS strobe to the data so the strobe latches in data during the valid data window.

The Read Gate Leveling parameters are used for DDR3 only. I think this subtle point was missed by the technical writers.

I will add this to the list of changes that need to be made to the manual.

With regards to question #2: It looks like two of the register are required for normal operations (CR39, CR41)

CR38 - This is a register that controls dynamic frequency scaling. This feature was not implemented in the silicon design of the chip, so this register should not be set. Leave as 0x00000000

CR39 - This register appears to be designated at "reserved" in error and needs to be updated. Specifically, bit fields [15:8] and [31:16] need valid parameters. Recommend a setting of 0x04001000

CR41 - This register also appears to be designated at "reserved" in error and needs to be updated. Specifically, bit field [0] needs to be set to 'b1. Recommend a setting of 0x00000001

CR125 - Sets timing parameters for a DLL_RST signal that is not used in the silicon. This register should not be set. Leave as 0x00000000.

CR131 - Sets a timing parameter that is not used in the Vybrid silicon. This register should not be set. Leave as 0x00000000.

These registers are further described in the Vybrid Register programming aid. Hopefully you have this. The Reference Manual re-wrtie was intented to remove useless information that was confusing customers. It seems that some of the section updates were mistakenly changed to "reserved".

Please change your code to include proper settings for CR105, CR110 and the recommended settings for CR39 and CR41 above. Please removed any reference to write to registers CR38, CR125 and CR131.

Confirm that these settings work for your board.

If they don't, reply back in this post and I will pursue the issue further. I'm sorry for the trouble this has caused.

Cheers,

Mark

CC: jiri-b36968

[ericaverill]

Mark,

Thanks, that helps but it does bring up some additional questions:

1. How do you determine the "correct" values to use in CR105 and CR110 (and the other DQ/DQS registers for that matter)? It seems like for DDR3 there is training and/or leveling that can help for this but that doesn't seem to be the case for LPDDR2. The Freescale spreadsheet also seems to indicate that there is a "stress test" that can help determine these settings, can that be run with LPDDR2? We currently have these fields (RDLVL_DL_0 in CR105(23:8) for example) set to 0x2020. This seems to indicate a delay of 64.25 clock cycles which doesn't seem correct but seems to be working today.

2. We have some other "magic" values being written into registers not applicable for LPDDR2, do these look correct?

     CR30 is being written with 0x0000000A.

     CR96 is being written with 0x00002819

     CR132 is being written with 0x00000305, the recommended value of 0x00000306 doesn't seem to work.

     CR156 is being written with 0x000000C0

[TheAdmiral]

Hi Eric,

To determine the values of CR105, CR106, CR110, PHY04 and PHY20, you can use Processor Expert for Vybrid found here:

Processor Expert Software, Microcontroller Dr|Freescale

CR30 is a DDR3 register only. The value programmed into this register should make no difference at all.

>> Are you saying you have a problem if this register is programmed to 0x00000000?

CR96 is a DDR3 register only. It controls "Write Leveling Calibration", which is a feature that can only be used by DDR3. If it is not enabled, none of the settings in this register have an impact.

>> Same question: Are you seeing a problem if this register is not 0x00000000?

CR132 definitely affects both DDR3 and LPDDR2. It adjust the controller for specific read and write latencies that may be peculiar to different LPDDR2 devices. So it is not unreasonable that this register needs to be adjusted to 0x00000305. Lower values will result in faster through put, but the values must be high enough to support the DRAM. Processor Expert does not provide an automatic means to test this register setting. You will just have to adjust it down to a setting that future testing proves reliable.

CR156 is a read only field. There should be no writes to this register, and any write will be ignored.

Cheers,

Mark

[ericaverill]

Thanks Mark, I have processor expert installed and am playing around with the memory controller settings. I will try to get everything configured in this environment and see if it gives me all of the settings and will post again if I have any further questions.

[ericaverill]

Mark,

Sorry it's been a while and I'm now trying to finally wrap this up. I believe I have all the registers except for CR105 and CR110. The fields you mentioned above in these registers are both set to 0x2020 which I believe comes from the tower configuration. Per the description in the datasheet however this would correspond to a delay of 64.25 clock cycles which does not seem correct. The datasheet does also not provide guidance for the setting of this register field. The register configuration spreadsheet I have indicates that a stress test should be used to find the correct value for this parameter however the DDRv tool only appears to be supported for 32-bit operating systems which we don't have available. Is there any guidance for setting this register value outside of the stress test program?

[antoniojenkins]

Eric,

How are you running the DDRv tool for Vybrid?  From what I can gather, it only works with CodeWarrior.  I have DDR3 running well with the Vybrid now, and I used ProcessorExpert to help me get all the "correct" values for all the control registers.  Now I would like to tune my settings with the DDRv tool.  Any help would be greatly appreciated.

[ericaverill]

Antonio,

Sorry I am not. Per my above post I believe it's only available for x32 systems which we don't have available. I also believe that there isn't one available for LPDDR2 on Vybrid which we are using so I haven't taken this any further.

[karina_valencia]

TheAdmiral can you continue with the follow up.?

[karina_valencia]

reminder

TheAdmiral can you continue with the follow up.?

[VilemZ]

Hi TheAdmiral,

can you help me with this thread?

Thank you

Vilem