Is it possible to disable the L2 once it has been enabled by the boot loader? Or is it only possible via e-fuse to avoid initialization during boot? How can I initialize the L2 manually?
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See the digit before N letter in part number. 1N - you have L2 cache and no RAM at 0x3f48xxxx , 0N - no L2 cache but 0.5MB RAM at 0x3f480000. You can't map L2 cache RAM to address space anyhow.
See the digit before N letter in part number. 1N - you have L2 cache and no RAM at 0x3f48xxxx , 0N - no L2 cache but 0.5MB RAM at 0x3f480000. You can't map L2 cache RAM to address space anyhow.
Dear Adam,
Regards, Naoum Gitnik.
The L2-cache controller is an l2c310_r3p2. The data sheet can be downloaded from the ARM web sight. From the documentation, the base physical address is 0x40006000. The controller is trustzone aware. To access everything, you must be in the secure supervisor modes. The Vybrid configuration has no data banking, no lock down by line/master and no parity. It is 64KB way size with 8 ways. The address 40006100 bit 0 will turn the L2 cache on and off. However, you might need to do some flushing and/or invalidation before doing this.
Edit: Also the MQX version of the cortex-A5 BSP/PSP has some code for manipulating the L2. There is also Linux source and header to handle several ARM L2 designs. The key is the Vybrid L2 register base is 0x40006000; it is in the memory map of the Vybrid software reference manual.