T1042 data sheet specifies a common mode of the DIFF_SYSCLK/DIFF_SYSCLK_B inputs as required to be 100 mV - 400 mV per section 3.22.2.3
However, the section 3.6.6 has a "receiver reference diagram of the Differential System clock" and shows an LVDS input buffering.
LVDS has typical common mode range of 1 - 1.2V, but T1042 specifies the common mode range of input clock to be 100 mV - 400 mV.
What is that standard that the DIFF_SYSCLK/DIFF_SYSCLK_B should be following? If the external clock is LVDS, what is proper way to terminate it for the T1042 since it seems to have an off common mode range requirement? Are AC coupling caps okay?
