Hi, Dear:
I'm developing T2080RDB-PC boards, and I have a bit of a problem when replacing the DDR3 memory card. The original DDR3L(D3XP56082XL10AA) can correctly identify memory under 1066Mhz/1600Mhz/1866Mhz, and the logs as follows:
“
U-Boot 2016.012.0+ga9b437f (Oct 26 2017 - 10:47:17 +0800)
initcall: eff4eee4
U-Boot code: EFF40000 -> F0000000 BSS: -> F004D4A0
initcall: eff4809c
CPU0: T2080E, Version: 1.1, (0x85380011)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1799.820 MHz, CPU1:1799.820 MHz, CPU2:1799.820 MHz, CPU3:1799.820 MHz,
CCB:599.940 MHz,
DDR:799.980 MHz (1599.960 MT/s data rate) (Asynchronous), IFC:149.985 MHz
FMAN1: 699.930 MHz
QMAN: 299.970 MHz
PME: 599.940 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 1206001b 15000000 00000000 00000000
00000010: 66150002 00000000 ec027000 c1000000
00000020: 00800000 00000000 00000000 000307fc
00000030: 00000000 00000000 00000000 00000004
initcall: eff4ebe0
initcall: eff4f088
I2C: Requested speed:100000, i2c_clk:299970000
FDR:0x34, div:5120, ga:0x4, gb:0x5, a:10, b:512, speed:58587
Tr <= 1566 ns
FDR:0x31, div:3072, ga:0x5, gb:0x4, a:12, b:256, speed:97646
Tr <= 713 ns
divider:2999, est_div:3072, DFSR:14
FDR:0x31, speed:97646
ready
initcall: eff4f904
Board: T2080RDB, Board rev: 0x01 CPLD ver: 0x03, boot from NOR vBank4
SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=100.00MHZ
SD2_CLK1=100.00MHZ, SD2_CLK2=100.00MHZ
initcall: eff4f048
SPI: ready
initcall: eff4f014
DRAM: initcall: eff4efb8
Initializing....using SPD
starting at step 1 (STEP_GET_SPD)
Requested speed:100000, i2c_clk:299970000
FDR:0x34, div:5120, ga:0x4, gb:0x5, a:10, b:512, speed:58587
Tr <= 1566 ns
FDR:0x31, div:3072, ga:0x5, gb:0x4, a:12, b:256, speed:97646
Tr <= 713 ns
divider:2999, est_div:3072, DFSR:14
FDR:0x31, speed:97646
DDR: DDR III rank density = 0x 80000000
Computing lowest common DIMM parameters for memctl=0
Detected UDIMM D3XP56082XL10AA
lowest_common_spd_caslat is 0xb
all DIMMs ECC capable
tCKmin_ps = 1071
trcd_ps = 13125
trp_ps = 13125
tras_ps = 34000
twtr_ps = 7500
trfc_ps = 160000
trrd_ps = 5000
twr_ps = 15000
trc_ps = 47125
Reloading memory controller configuration options for memctl=0
mclk_ps = 1250 ps
Found timing match: n_ranks 2, data rate 1600, rank_gb 2
clk_adjust 5, wrlvl_start 8, wrlvl_ctrl_2 0x808070b, wrlvl_ctrl_3 0xc0d0e0a
0 of 1 controllers are interleaving.
Checking interleaving options completed
dbw_cap_adj[0]=0
ctrl 0 dimm 0 base 0x0
ctrl 0 total 0x100000000
Total mem by __step_assign_addresses is 0x100000000
Total mem 4294967296 assigned
FSL Memory ctrl register computation
FSLDDR: cs[0]_bnds = 0x000000ff
FSLDDR: cs[0]_config = 0x80044302
FSLDDR: cs[0]_config_2 = 0x00000000
FSLDDR: cs[1]_bnds = 0x000000ff
FSLDDR: cs[1]_config = 0x80004302
FSLDDR: cs[1]_config_2 = 0x00000000
FSLDDR: cs[2]_bnds = 0x00000000
FSLDDR: cs[2]_config = 0x00000000
FSLDDR: cs[2]_config_2 = 0x00000000
FSLDDR: cs[3]_bnds = 0x00000000
FSLDDR: cs[3]_config = 0x00000000
FSLDDR: cs[3]_config_2 = 0x00000000
FSLDDR: timing_cfg_0 = 0x5011010c
FSLDDR: timing_cfg_3 = 0x01071000
FSLDDR: timing_cfg_1 = 0xbcb48c46
FSLDDR: timing_cfg_2 = 0x0040c156
FSLDDR: ddr_cdr1 = 0x80040000
FSLDDR: ddr_cdr2 = 0x00000001
FSLDDR: ddr_sdram_cfg = 0xc7054000
FSLDDR: ddr_sdram_cfg_2 = 0x24401100
FSLDDR: ddr_sdram_mode = 0x00441c70
FSLDDR: ddr_sdram_mode_3 = 0x00001c70
FSLDDR: ddr_sdram_mode_5 = 0x00001c70
FSLDDR: ddr_sdram_mode_5 = 0x00001c70
FSLDDR: ddr_sdram_mode_2 = 0x00980000
FSLDDR: ddr_sdram_mode_4 = 0x00980000
FSLDDR: ddr_sdram_mode_6 = 0x00980000
FSLDDR: ddr_sdram_mode_8 = 0x00980000
FSLDDR: ddr_sdram_interval = 0x0c30030c
FSLDDR: clk_cntl = 0x03000000
FSLDDR: timing_cfg_4 = 0x00000001
FSLDDR: timing_cfg_5 = 0x04401400
FSLDDR: zq_cntl = 0x89080600
FSLDDR: wrlvl_cntl = 0x8675f608
FSLDDR: wrlvl_cntl_2 = 0x0808070b
FSLDDR: wrlvl_cntl_3 = 0x0c0d0e0a
Programming controller 0
total 4 GB
Need to wait up to 66 * 10ms
setup ddr law base = 0x0, size 0x100000000, TRGT_ID 0x10
total_memory by __fsl_ddr_sdram = 4294967296
total_memory by __fsl_ddr_sdram = 4294967296
2 GiB left unmapped
initcall: eff4f2fc
Monitor len: 0010D4A0
Ram size: 00000000
Ram top: 80000000
Reserving MP boot page to 7ffff000
initcall: eff4ec2c
initcall: eff4ec40
initcall: eff4ee68
Reserving 1077k for U-Boot at: 7fef0000
initcall: eff4ee08
have goto reserve_malloc steps before!
Reserving 4104k for malloc() at: 7faee000
have goto reserve_malloc steps after!
initcall: eff4ef24
have goto reserve_board steps before!
sizeof(bd_t) = 72 Bytes, gd->start_addr_sp = 7faedfb8!
Reserving 72 Bytes for Board Info at: 7faedfb8
have goto reserve_board steps after!
initcall: eff4edd4
have goto setup_machine steps!
initcall: eff4ed70
have goto reserve_global_data steps before!
Reserving 192 Bytes for Global Data at: 7faedef8
have goto reserve_global_data steps after!
initcall: eff4ece8
initcall: eff4eca0
initcall: eff4f3cc
initcall: eff4f2bc
initcall: eff4f26c
4 GiB (DDR3, 64-bit, CL=11, ECC off)
DDR Chip-Select Interleaving Mode: CS0+CS1
”
But when I change the memory card to DDR3(RMT3150ED58E8W1600), the u-boot stopped and hanged. The log as follows:
“
U-Boot 2016.012.0+ga9b437f (Oct 26 2017 - 10:47:17 +0800)
initcall: eff4eee4
U-Boot code: EFF40000 -> F0000000 BSS: -> F004D4A0
initcall: eff4809c
CPU0: T2080E, Version: 1.1, (0x85380011)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1799.820 MHz, CPU1:1799.820 MHz, CPU2:1799.820 MHz, CPU3:1799.820 MHz,
CCB:599.940 MHz,
DDR:799.980 MHz (1599.960 MT/s data rate) (Asynchronous), IFC:149.985 MHz
FMAN1: 699.930 MHz
QMAN: 299.970 MHz
PME: 599.940 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 1206001b 15000000 00000000 00000000
00000010: 66150002 00000000 ec027000 c1000000
00000020: 00800000 00000000 00000000 000307fc
00000030: 00000000 00000000 00000000 00000004
initcall: eff4ebe0
initcall: eff4f088
I2C: Requested speed:100000, i2c_clk:299970000
FDR:0x34, div:5120, ga:0x4, gb:0x5, a:10, b:512, speed:58587
Tr <= 1566 ns
FDR:0x31, div:3072, ga:0x5, gb:0x4, a:12, b:256, speed:97646
Tr <= 713 ns
divider:2999, est_div:3072, DFSR:14
FDR:0x31, speed:97646
ready
initcall: eff4f904
Board: T2080RDB, Board rev: 0x01 CPLD ver: 0x03, boot from NOR vBank4
SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=100.00MHZ
SD2_CLK1=100.00MHZ, SD2_CLK2=100.00MHZ
initcall: eff4f048
SPI: ready
initcall: eff4f014
DRAM: initcall: eff4efb8
Initializing....using SPD
starting at step 1 (STEP_GET_SPD)
Requested speed:100000, i2c_clk:299970000
FDR:0x34, div:5120, ga:0x4, gb:0x5, a:10, b:512, speed:58587
Tr <= 1566 ns
FDR:0x31, div:3072, ga:0x5, gb:0x4, a:12, b:256, speed:97646
Tr <= 713 ns
divider:2999, est_div:3072, DFSR:14
FDR:0x31, speed:97646
DDR: DDR III rank density = 0x 80000000
Computing lowest common DIMM parameters for memctl=0
Detected UDIMM RMT3150ED58E8W1600
lowest_common_spd_caslat is 0xb
Warning: not all DIMMs ECC capable, cant enable ECC
tCKmin_ps = 1250
trcd_ps = 13125
trp_ps = 13125
tras_ps = 35000
twtr_ps = 7500
trfc_ps = 160000
trrd_ps = 6000
twr_ps = 15000
trc_ps = 48125
Reloading memory controller configuration options for memctl=0
mclk_ps = 1250 ps
Found timing match: n_ranks 1, data rate 1600, rank_gb 2
clk_adjust 5, wrlvl_start 8, wrlvl_ctrl_2 0x808070b, wrlvl_ctrl_3 0xc0d0e0a
0 of 1 controllers are interleaving.
Checking interleaving options completed
dbw_cap_adj[0]=0
ctrl 0 dimm 0 base 0x0
ctrl 0 total 0x80000000
Total mem by __step_assign_addresses is 0x80000000
Total mem 2147483648 assigned
FSL Memory ctrl register computation
FSLDDR: cs[0]_bnds = 0x0000007f
FSLDDR: cs[0]_config = 0x80044302
FSLDDR: cs[0]_config_2 = 0x00000000
FSLDDR: cs[1]_bnds = 0x00000000
FSLDDR: cs[1]_config = 0x00000000
FSLDDR: cs[1]_config_2 = 0x00000000
FSLDDR: cs[2]_bnds = 0x00000000
FSLDDR: cs[2]_config = 0x00000000
FSLDDR: cs[2]_config_2 = 0x00000000
FSLDDR: cs[3]_bnds = 0x00000000
FSLDDR: cs[3]_config = 0x00000000
FSLDDR: cs[3]_config_2 = 0x00000000
FSLDDR: timing_cfg_0 = 0x5011010c
FSLDDR: timing_cfg_3 = 0x01071000
FSLDDR: timing_cfg_1 = 0xbcb48c56
FSLDDR: timing_cfg_2 = 0x0040c158
FSLDDR: ddr_cdr1 = 0x80040000
FSLDDR: ddr_cdr2 = 0x00000001
FSLDDR: ddr_sdram_cfg = 0xc7050000
FSLDDR: ddr_sdram_cfg_2 = 0x24401100
FSLDDR: ddr_sdram_mode = 0x00441c70
FSLDDR: ddr_sdram_mode_3 = 0x00001c70
FSLDDR: ddr_sdram_mode_5 = 0x00001c70
FSLDDR: ddr_sdram_mode_5 = 0x00001c70
FSLDDR: ddr_sdram_mode_2 = 0x00980000
FSLDDR: ddr_sdram_mode_4 = 0x00980000
FSLDDR: ddr_sdram_mode_6 = 0x00980000
FSLDDR: ddr_sdram_mode_8 = 0x00980000
FSLDDR: ddr_sdram_interval = 0x0c30030c
FSLDDR: clk_cntl = 0x03000000
FSLDDR: timing_cfg_4 = 0x00000001
FSLDDR: timing_cfg_5 = 0x04401400
FSLDDR: zq_cntl = 0x89080600
FSLDDR: wrlvl_cntl = 0x8675f608
FSLDDR: wrlvl_cntl_2 = 0x0808070b
FSLDDR: wrlvl_cntl_3 = 0x0c0d0e0a
Programming controller 0
total 2 GB
Need to wait up to 32 * 10ms
setup ddr law base = 0x0, size 0x80000000, TRGT_ID 0x10
total_memory by __fsl_ddr_sdram = 2147483648
total_memory by __fsl_ddr_sdram = 2147483648
initcall: eff4f2fc
Monitor len: 0010D4A0
Ram size: 80000000
Ram top: 80000000
Reserving MP boot page to 7ffff000
initcall: eff4ec2c
initcall: eff4ec40
initcall: eff4ee68
Reserving 1077k for U-Boot at: 7fef0000
initcall: eff4ee08
have goto reserve_malloc steps before!
Reserving 4104k for malloc() at: 7faee000
have goto reserve_malloc steps after!
initcall: eff4ef24
have goto reserve_board steps before!
sizeof(bd_t) = 72 Bytes, gd->start_addr_sp = 7faedfb8!
”
I tried 1066Mhz and 1600Mhz, changed the SWITCH SETTING SW2[7] to 0(ON), and connect the Jumper J27(1.5V). And I tried all the DDR_DDR_SDRAM_CLK_CNTL phases. The phenomenon is the same.
And I tried to set DDR_TIMING_CFG_2[WR_DATA_DELAY] to 1/2 clock delay, it would not work too.
The Differences between these memory card is as followed:
And I think the T2080 ddr registers are setup automatically by reading eeprom in memory card.
It's been two weeks since I got stuck in this problem, and the memory card is fine. What is the problem?The Complete logs see attachments.
Looking forward to your reply.
Yours Yang
解決済! 解決策の投稿を見る。
Hi:
I just only exchanged the T2080RDB-PC's memory card! Then, It can not work any more, What can I do now?
Hi:
I just only exchanged the T2080RDB-PC's memory card! Then, It can not work any more, What can I do now?
Your dump shows problem about ECC using for new DIMM. Test your board if ECC is enabled in the u-boot. Comment CONFIG_DDR_ECC variable in the /include/configs/T208xRDB.h file.
Have a great day,
Pavel Chubakov
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Dear Pavel:
Thanks for your reply. My new memory card(RMT3150ED58E8W1600) doesn't support the ECC. So I disabled the CONFIG_DDR_ECC variable. I have tried a lot of register combinations, however it does't work yet!
Have a good day! Yours Yang
Hi
The project is very urgent. Can someone provide help as soon as possible?
yours Yang