T1042 SerDes Options: SATA on LaneG

[stefanlange]

Hello NXP team,

we have designed a T1042 module with a starterkit and would like to test the SATA interface on SerDes Lane G.

TQMT1040RM Rev0 figure 31-1 on page 1723 shows the supported SerDes options.

Option 0x88 would be the relevant one for us in this case.

However upon setting the RCW SRDS_PRTCL_S1 bits to 0x88, UBoot prints:

Corenet Platform Cache: 256 KiB enabled

Using SERDES1 Protocol: 136 (0x88)

SERDES1[PRTCL] = 0x88 is not valid

..

Looking at the UBoot code in

arch/powerpc/cpu/mpc85xx/t1040_serdes.c

I noted that 0x88 is not an option in the serdes_cfg_tbl:

static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {

  [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,

  PCIE2, PCIE2, PCIE2, PCIE2},

  [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,

  PCIE2, PCIE3, PCIE4, SATA1},

  [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,

  PCIE2, PCIE3, SATA2, SATA1},

  [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  PCIE2, PCIE2, PCIE2, PCIE2},

  [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,

  PCIE2, PCIE2, PCIE2, PCIE2},

  [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,

  PCIE2, PCIE3, PCIE4, SATA1},

  [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,

  PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},

  [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,

  PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},

  [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  PCIE2, PCIE3, PCIE4, SATA1},

  [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},

  [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},

  [0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,

  PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},

  [0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,

  PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},

  [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},

  [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},

  [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},

  [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

  PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},

};

Is there a particular reason for this, have I overread something in the reference manual?

Please advise.

Thanks and best regards,

Stefan

[stefanlange · Accepted solution]

Hey all,

I received following Response from the Applications Team:
"This is not an erratum.
The only thing is that SDK only  enables and tests certain protocols. This is mainly governed by RDB board.

Hence this protocol is missing from the t1040_serdes.c file.

Having said that the above file may have more protocols which they could test on QDS; or some untested as well.
But this file does not have all the protocols which the SoC supports."

I modified the respective file as follows, and it worked for me. I was able to use an attached SATA drive on this SerDes Lane in Linux.

diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c

index d5dccd5..c3ea10e 100644

--- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c

+++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c

@@ -33,6 +33,8 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {

                PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},

        [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

                PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},

+       [0x88] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

+               PCIE2, PCIE3, SATA2, SATA1},

        [0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,

                PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},

        [0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,

[ufedor]

Please refer to the T1040RM Rev1.

[stefanlange]

TQMT1040RM Rev1 figure 31-1 on page 1721

[stefanlange]

Do you need any additional information?

Best regards,

Stefan

[ufedor]

No additional information is required.

Currently the issue is escalated a higher support level and there is no response yet.

Please note that it will be more convenient to handle such kind of issues as technical cases:

How I could create a Service Request?