T1040RDB DIP switch available for personal use?

[mathiasparnaude]

Hello

I have few questions regarding DIP switches on the T1040RDB board:

1. Is it possible to read their status from U-Boot (even writing some code)?

2. Is there at least an unused switch or reserved for personal use? I think about TEST_SEL_N (SW3[8]), I am not aware of what it does.

I would like to control the U-Boot start in two different modes (implement one action or another is the switch is off or on).

If that is not possible this way, is there any other possibilities? How?

Thanks!

[LPP · Accepted solution]

2.

T1040 IFC_AD[0:7] general-purpose inputs are available for application-specific use.

The encoded values latched on these signals during POR are accessible in GPPORCR1[POR_CFG_VEC].

However, T1040RDB design doesn't use this function.

Configuration switches on T1040RDB are all allocated for purpose. You can't use them otherwise.

TEST_SEL_N is critical signal and it must be used as defined by the datasheet:

"Note 23. This pin must be pulled to O1VDD through a 100-ohm to 1k-ohm resistor for a 4 core

T1040 and tied to ground for a 2 core T1020 device."

Have a great day,
Pavel

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[mathiasparnaude]

Thank you for your answers. I see ... that I can't realize what I expected to do. lunminliang: my idea was to choose by hardware (with the help of U-Boot) to enable or disable ECC for the purpose of my work.

[lunminliang]

Hello Mathias Parnaudeau,

1. Is it possible to read their status from U-Boot (even writing some code)?

Some of the SW could be read from CPLD registers, for example SW3[4] and SW3[5:7], which are BOOT_FLASH_SEL and CFG_VBANK[0:2], those could be read from the flash control and status register (FLHCSR), at offset 13h, FLHCSR[BOOT_SEL] and FLHCSR[SW_BANK_SELn].

The CPLD is on local bus with address 0xffdf0000.

I would like to control the U-Boot start in two different modes

What mode would you like U-Boot to start?

Have a great day,

Lunmin

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